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clock
- 用 Verilog HDL 设计一个多功能数字钟，包含以下主要功能： 1） 计时，时间以 24 小时制显示； 2） 校时； 3） 闹钟：设定闹钟时间，可利用 LED 闪烁作为闹钟提示； 4） 跑表：启动、停止； 5） 其他。-Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed
test12
- 自己用VerilogHDL语言编写的时钟程序，包括时钟进位计数模块，数码管显示模块和闹钟模块。在cpld芯片上经测试有效（开发环境没找到VerilogHDL，就选了VHDL，其实他们不一样的……）-Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been te
num_clock
- 基于DE0实验板开发的verilog数字钟程序。实现了12/24小时制切换；闹钟；整点报时等功能。-Based on experimental board development DE0 verilog digital clock procedures. To achieve a 12/24 hour switch alarm clock whole point timekeeping function.
digitalclock
- digital alarm clock on lcd- written in verilog to program fpga or cpld
electronic-clock
- verilog电子时钟，可以实现复位、计时、校时、闹钟等多种功能。-verilog electronic clock, you can achieve a variety of functions reset, time, school, alarm clock and so on.
clock
- verilog的数字钟代码，在XILINX上运行，可以手动设置时钟、闹钟，可报警-digital clock verilog code running on XILINX, you can manually set the clock, Alarm Clock, alarm
passlock
- 采用verilog编写的4位密码锁，输入4位密码，带有返回重新输入功能，经过确定验证后，如果密码正确，则发出灯亮，如果错误则蜂鸣器报警。通过实验-Using verilog written four locks, enter the 4-digit password, after determining verify if the password is correct, then the issue lights, the buzzer alarm if an error. Experimen
clock_display
- 自己用verilog语言编写的数字钟程序，能在Alter公司的DE0板上完美运行，能时间计时，日期，闹钟，秒表的功能。 欢迎交流学习。-The digital clock program which developed by verilog language can run at Alter DE0 board, to the time time, date, alarm clock, stopwatch function.
clock
- 采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能： 1)计时功能：包括小时、分钟、秒钟。 2)校时功能：对小时、分钟和秒钟进行手动校时。 3)定时和闹钟功能：能在手工设定的时间产生闹铃音。 -Using synthesizable Verilog coding a digital clock with alarm. It has the following features: 1) timing functions include: hours, m
clock
- 用Verilog编程设计出一个具有计时，校准，闹钟，日历等功能的电子时钟； -Design a program with Verilog have time, calibration, alarm clock, calendar and other functions of electronic clock
shizhong
- 基于Verilog语言的时钟功能，具有调节时间，闹钟等功能-Verilog language-based clock function, regulate the time, alarm clock and other functions
rtcclock_latest.tar
- 国外的时钟以及闹钟和秒表功能的verilog程序，功能完善，具有一定是学习价值-The clock and alarm clock and stopwatch function Verilog program, perfect function, have a certain value of learning
clock
- 原创数字钟verilog程序，能实现数字钟基本功能，如：计数，跑表，定时，闹钟。用于ISE软件。-Original digital clock verilog procedures, to achieve the basic functions of digital clock, such as: counting, stopwatch, timer, alarm clock.
Clock-generator
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置-.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings
beep
- 用verilog实现的蜂鸣器报警，实现摩斯码报警。-Using Verilog to achieve the buzzer alarm, the realization of Moss code alarm.
baseonFPGAclock
- 用verilogHDL语言写的基于FPGA的电子钟。里面包含闹钟、秒表、日历、时间设置等功能，可用LCD显示-verilog language, implemented on the FPGA alarm clock, calendar, time display, stopwatch in one of the electronic clock and calendar. Can be displayed on LCD
boomshakalaka
- Verilog实现数字钟，超多功能，移位显示，闹钟设置，移位设置时间，定时秒表，控制LED记录数值等-Verilog digital clock, ultra-versatile, shift display, alarm settings, set the time shift, the timing stopwatch, and other numerical control LED record
clock
- Verilog实现时钟和闹钟功能，可以设置初始时间，调节时间。-Verilog realize the clock and alarm clock function, you can set the initial time, adjust the time.
digital_clock
- 基于vivado的FPGA数字闹钟的程序，verilog语言编写-Vivado based on the FPGA digital alarm clock procedures, verilog language
clock
- 基于verilog简易数字钟，能够做到计时，闹钟，倒计时等功能。(Based on Verilog simple digital clock, can achieve time, alarm clock, countdown and other functions.)