搜索资源列表
CPU
- RC4 Encrpytion 1.Encrpyt strings 2.Create pairs of keys for encoding and decoding automatically 3.Present the crptograph 4.Decode the crptograph to get the plaintext -This CPU has basic instruction set, and we utilize its instruction set
yetert
- This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).
ALU
- ALU design in Vhdl. Arithmetic Logic Unit
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
alu_struct
- ALU written in VHDL, tested in FPGA advantage, there will be no support on this code. All right reserved by developer.
micro
- 16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
2bit_ALU
- This is a source code of 2 bit ALU and this is in VHDL form.-This is a source code of 2 bit ALU and this is in VHDL form.
VHDl
- Its a ALU code for the mathematical computations.It also has many other codes.
hcsa_adder_latest(2).tar
- Hierarchical Carry Save Algorithm. HCSA Generic ALU.
alu
- 描述乘法器，组成原理vhdl实现一位乘法器程序代码-Describe the multiplier, the composition principle to achieve a multiplier vhdl code
project
- 利用VHDL实现三个简单的程序：BCD加法器；ALU算术逻辑单元；简单密码锁设计，具有输入密码和数据比较两种功能，由M决定是写入还是开锁。而数据写入是采用列地址与输入数相结合的的方法，存入初始密码；开锁时，密码以输入，再输入的数据逐个与输入的一组数据比较，完全吻合则开锁。-The use of VHDL to accomplish three simple procedures: BCD adder ALU arithmetic logic unit simple lock design,
ALUALUcontrol
- 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
ALU
- vhdl code for alu and detemines the basic components of alu unit in cpu system
alu_project
- ALU using VHDL project
ALU.vhd
- Desarrollo de la Unidad Légica Aritmética (ALU) en VHDL
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
Alu
- 4位ALU逻辑运算器，用VHDL语言编写-4-bit ALU process using VHDL
ALU
- VHDL code for 3 bit ALU
alu
- 加法器源码 CPU设计专用 VHDL实现-Source adder VHDL CPU designed to achieve specific
alu32
- 32 bit ALU design using VHDL code for Xilinx ISE Foundation