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axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
MEM_Array
- vivado HLS中自定义axi4接口的实现(Implementation of custom axi4 interface in vivado HLS)
new.v
- 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)
Custom_AXI_IP_For_Vivado_IP_Integrator
- 使用 VIVADO 工具简单高效的创建AXI接口的ip，支持 AXI4LITE, AXI4-STREAM, AXI4-FULL 可方便的实现IP间互联(Use VIVADO tool to create AXI interface IP simply and efficiently, and support AXI4LITE, AXI4-STREAM, AXI4-FULL to facilitate IP interconnection.)
AXI4_specification
- AXI总线规格书，用于AXI总线开发的必备资料(AXI specification which is the best stuff for development in terms of AXI bus and so on)
Multi-Channel PCe QDMA&RDMA Subsystem
- 基于PCI Express Integrated Block，Multi-Channel PCIe QDMA&RDMA Subsystem实现了使用DMA地址队列和DMA Ring缓冲的独立多通道、高性能Continous或Scather Gather DMA，提供FIFO/AXI4-Stream用户接口。 特性： 支持Ultrascale+，Ultrascale，7 Series的PCI Express Integrated Block 支持64，128，256，512