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hdlc_latest[1]
- HDLC解码控制,包括CRC校验,可以在一片3400A FPGA上实现8解码-HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
cic
- 五阶CIC梳状积分滤波器,可以综合,非常有参考价值-Fifth-order CIC points comb filter, can be integrated and very useful
FPGA_VHDL_code
- FPGA学习非常珍贵的资料,包括USB、UART、I2C、Ethernet、VGA、CAN等总线的VHDL实现,可以直接应用于实际项目中。需要的请下载。 -FPGA to learn very valuable information, including USB, UART, I2C, Ethernet, VGA, CAN bus, such as VHDL to achieve, can be directly applied to actual projects. Need to do
VHDL_code
- 基于FPGA的AD,DA,LCD,LED,CAN,I2C,PS2,VGA以及一些通讯ASK,FSK等的VHDL源程序,所有程序已通过调试,需要的拿走。-FPGA-based AD, DA, LCD, LED, CAN, I2C, PS2, VGA, and some communications ASK, FSK, etc. VHDL source code, all procedures have been debugging, need to take.
EP1C3_12_5_RSV
- 基于FPGA的数字存储示波器,用VHDL实现的,压缩包里是Quartus工程。AD采样送进FPGA,存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
H.264Decoder
- H.264解码器,用verilog写成,可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
FPGAPLL
- FPGA做的PLL 可以使用,比软件自带的省一些资源-PLL can be used FPGA to do more than the software comes with some of the resources of the province,
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
RS485EN
- RS485的双向通信处,正在为此头疼的同学们可要注意了,这个可以解决你们双向通信过程中的很多问题哦-Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码,可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
FPGA_common_idea
- 本文讨论的四种常用FPGA/CPLD 设计思想与技巧:乒乓操作、串并转换、流水线操作、数据接口同步化,都是FPGA/CPLD 逻辑设计的内在规律的体现,合理地采用这些设计思想能在FPGA/CPLD 设计工作种取得事半功倍的效果。-This article discusses the four commonly used FPGA/CPLD design ideas and techniques: ping-pong operation, strings, and conversion, pipe
fft
- FPGA控制串行AD(AD0804),状态机实现,可以根据该程序实现数字电压计,数字温度计的设计-FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
CyclonePLL
- Cyclone™ FPGA具有锁相环(PLL)和全局时钟网络,提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出,进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件,就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟,使内部工作的时钟频率比外部时钟更高,时钟延迟和时钟偏移最小,减小或调整时钟
DAC8812
- DA转换,Verilog HDL 编的,可实现DA转化。DA芯片用的是DAC8812,实现16位数模转化。-DA conversion, Verilog HDL code, the DA conversion can be achieved. DA-chip using a DAC8812, 16-bit analog-to achieve transformation.
lcom
- 很经典的单片机程序,可以实现单片机与FPGA的通信-Is the classic single-chip process can be achieved with single-chip FPGA communications
password_lock
- 电子密码锁,采用基于fpga的设计,可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password
DDS
- 利用FPGA的资源实现任意波形的产生,再若和单片机配合就能做成任意的波形发生器。-Use of FPGA resources for the realization of arbitrary waveform generation, again if and SCM can be made with the arbitrary waveform generator.
FPGA
- fpga初学者的一个不错的入门,可以从总体上认识fpga的各项特点和功能。-FPGA beginners a good entry, you can generally understand the FPGA from the various features and functions.
clock
- 数字钟设计,有分秒显示,上下午显示,可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh