搜索资源列表
I486bus
- 基于VHDL语言开发的I486总线接口程序。实现了一个三态的总线，可保证数据的正常传输。-based on VHDL development of the I486 bus interface procedures. Implementation of a three-state bus can ensure that the normal data transmission.
i2c_cores
- IIC总线协议，VHDL语言编写，可以直接使用-IIC bus protocol, VHDL language can be used directly
vga_card
- VGA模块的VHDL代码和软件驱动，可作为外设挂接在Avalon总线上。用一块SRAM作为显存，双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
i2c_p_altera
- Alter 公司的I2C总线协议 VHDL语言实现 附有详细的说明 可以直接调用-Alter the company of I2C bus agreement VHDL language realization with detailed instructions can directly calls
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
oc_i2c_master
- IIC总线的控制VHDL源代码以及说明，在Quartus2中能够生成对应的IP核-the IIC bus control VHDL source code and ，Quartus2 can create the corresponding IP in nuclear
I2Ctestwrite
- sopc读写i2c总线的程序，可以模块化调用。vhdl语言编写。-sopc i2c bus read and write the program, you can call the modularity. vhdl language.
verilog
- 都是介绍VHDL的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
The--VHDL-code-of-I2C
- 该程序采用延时接收比较来实现仲裁的方法，使不具有I2C接口的普通微控制器（MCU）能够实现模拟I2C总线的多主通信。-This program is to realize the delay receiving the arbitration method, do not have the I2C interface of ordinary micro controller (MCU) can simulate the I2C bus more than the main communicati
I2C_EPM3128(v1.00)
- 本程序是使用 VHDL 语言开发的， 能够实现ALTERA CPLD-EPM3128A 通过I2C总线对EEPROM的读写。-This program is developed using VHDL language can of ALTERA CPLD-EPM3128A through the I2C bus EEPROM read and write.
sIP__SPIIp
- spi总线的vhdl代码，试了了试能用。希望能对开发者有所帮助。 -spi bus vhdl code, try the test can be used. The hope is to help developers.
fVerrilog_Devr
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
can_latest.tar
- can总线的FPGA实现，代码为VHDL，逻辑清晰，代码规范-FPGA implementation can bus, code for VHDL, clear logic and code specifications
a_vhdl_can_controller
- 使用VHDL语言编写的CAN总线控制器程序，经过编译和波形仿真验证。可以为大家提供一个参考。-Using VHDL language CAN bus controller program, compiled and waveform simulation. Can provide a reference for everyone.
a_vhdl_can_controller_latest.tar
- CAN 总线的IP核，采用VHDL语言编写。适用各类FPGA-CAN bus IP core, using VHDL language. Apply to the various FPGA
axi_master_latest.tar
- axi 总线 设计 和 仿真， 可以在设计中直接运动， 提供完整源代码和仿真文件， 用vhdl 语言实现。-axi bus design and simulation, you can directly exercise in design, providing full source code and simulation files, using vhdl language.
ReadWrite-RAM-VHDL-source-code
- This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus