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calendar
- 这是用Verilog写的万年历，里面包含的日月年各个模块。各个模块用Verilog写的，最后用原理图把各个模块组装成最终的系统。每个模块经过仿真没有问题，整个工程在板子上经过试验，能够完成万年历的功能。-This is the calendar write with Verilog, contains the sun and the moon years each module. Each module in Verilog written, finally the principle diag
PS2_keyboard_driver
- verilog写的键盘按键扫描接口，并在7段数码管上显示断码和通码，在LED流水灯上实现滚动显示。想学习PS2键盘扫描这块的童鞋可以下载看看，代码写的还行。-verilog to write a keyboard key scan interface displayed on the 7-segment digital tube broken code and pass code, scrolling display on the LED light water. Want to learn a
verilogcalculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator, addition, subtraction operation can be realized using verilog prepared
Frequency-tester
- 数字频率计，能自动测试输入方波脉冲的频率，通过LCD1602显示，是用Verilog HDL写的-Digital frequency measurement，Can automatic testing input square wave pulse frequency, through the LCD1602 shows, it is to use Verilog HDL write
syn_detc
- Verilog语言的同步帧检测模块，适用于pcm通信系统，本模块可检测的同步帧为100110-The synchronization frame detection module implemented use Verilog language,for pcm communication system, the module can detect synchronization frame for 10,011,011
Channel_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
IFFT11111
- 使用Verilog编写的IFFT，ISE12.2下编译通过，学习IFFT核的同学可以参考-Use of the IFFT in Verilog compiler, ISE12.2 under study IFFT core students can refer to
Phase1111_Tracking
- 使用Verilog编写的相位跟踪器，可以有效解决锁相环中的相位跟踪问题，ISE12.2下编译通过-Written in Verilog phase tracker can effectively resolve the PLL phase tracking, ISE12.2 compiled by
FPGA_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
vga_dis
- verilog语言实现VGA接口显示，可以在显示器上显示几种图片，可以直接在quartus2上运行-verilog language display, VGA interface can display several pictures on the monitor, you can run directly in quartus2
DDDCCT_IDCTi
- 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包含VHDL及及Verilog版本。可用途JPEG及MEPG压缩算法 已通过测试。 -The discrete cosine transform and inverse discrete cosine transform HDL code and test files. Contains VHDL and Verilog versions. Can use JPEG and MEPG compression of algorithm has
UART_verilog
- 电脑发数据，CPLD接收后会送电脑的，verilog程序，可以直接使用-Computer to send data, the CPLD will be sent after receiving the computer, Verilog program can be used directly
adder
- 可加可减器，使用verilog编写，4位加减器。-Can be increased or decreased, verilog prepared 4 addition and subtraction.
135EGs_of_Verilog
- 135个Verilog经典程序，初学者可以多-135 Verilog classic program, beginners can see more
vds_proc
- 某知名外企公司解禁verilog代码。主要功能是视频显示处理等控制。可以综合。-A well-known foreign companies lifted the verilog code. The main function is the video display processing and control. Can be integrated.
fifo_ctrl
- 好用的fifo控制verilog源代码，供大家学习参考，可以被综合。-Useful fifo control verilog source code for the study reference, can be integrated.
firfilt
- FIR滤波器verilog源代码，经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
modetect
- 视频输入处理中的模式识别的verilog代码。经fpga验证，可以使用-Video input processing, pattern recognition verilog code. Fpga verification, you can use the
modedetct
- 功能强大的视频输入信号的模式识别verilog代码。可以综合，希望对大家有帮助-Powerful video input signal pattern recognition verilog code. Can be integrated, we hope to
vbi_proc
- 视频处理相关的verilog代码，可以实现在blank期间插入，其他有用信息。可以被综合。-Video processing, the verilog code can be inserted in the blank period, and other useful information. Can be integrated.