搜索资源列表
i2c
- 大公司解禁的I2C相关的verilog代码。可以被综合。-Large companies lifted the I2C Verilog code. Can be integrated.
led_seq_demo
- 跑马灯的打包verilog程序，包括v和ucf,以及能直接下载的xise文件-The Marquee verilog program package, including v and ucf, and can be downloaded directly xise file
filter_dds_10.29_7.2
- 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
can_verilog_IP.tar
- 运用Verilog语言编写的CAN控制IP核，符合CAN2.0B协议，仅作为参考！-CAN controller IP core using Verilog language, in line with CAN2.0B agreement, only as a reference!
IVerrilog_HDDn
- Verilog HDL入门，学习习的最好参考资料，能极短的时间内学会 -Verilog HDL entry, learning the best reference for learning, can be a very short period of time to learn to
klc_iic
- 基于I2C接口的的从机verilog代码，带子地址的发送方式，已下FPGA板子调通，大家可以借鉴。-Based on the I2C interface of the Verilog code, the tape address to send the next FPGA board tune pass, we can learn from.
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘（Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现，通过Modelsim软件对相应的波形进行仿真验证，并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be a
011-clk_div_pro
- verilog写的一个分频器，利用控制字累加方式，经测试可用-verilog to write a crossover, the control word can be used incrementally, tested
012-fre_tst
- verilog写的频率计，利用在一周期内计数方式，测试可用，500KHZ以上误差大-verilog to write the frequency meter, the test can be used
ROM_RTL
- Verilog Source File In the Quartus10.0 can be run this source code.
MIPS_final-version
- 以Verilog所撰寫的Booth’s Algorithm Multiplier，可加到NiosII CPU之上，完成一道NiosII CPU的新指令。-Written by Verilog Booth,' s Algorithm Multiplier can be added to the above NiosII CPU to complete a the Nios II CPU command.
S6_LCD_V
- 学习LCD的程序，可以运行，对学习verilog很有帮助。-Learning the procedures of the LCD, you can run, very helpful for learning verilog.
S11_USB
- 学习USB编程，可以运行，对学习verilog很有帮助-Learning the USB programming, you can run, be helpful to learn verilog
T6_SRAM
- 学习SRAM编程，可以运行，对学习verilog很有帮助-Learning SRAM programming, you can run verilog helpful in learning
Mstateei
- 米勒解码器的状态转换模块。用verilog语言编写写，ISE为开发环境 ，经测试可直接使用。 -Miller decoder state transition module. Verilog language writing, ISE development environment has been tested and can be used directly.
signal_generator
- 信号发生器 可以通过该程序产生对应的波形 用Verilog语言编写实现 希望能对大家有帮助-The signal generator can generate through the program corresponding to the waveform using the Verilog language
clock_2
- verilog hdl 时钟程序，数码管显示，并可设置闹钟-verilog hdl clock program, the digital display, and can set the alarm
demo110
- 状态机，检测状态110，小演示程序，可直接运行，verilog hdl-State machine, the detection state 110, a small demo program can be run directly, verilog hdl
dds_project
- DDS直接数字频率合成器，能产生正弦波，方波，锯齿波，三角波四种波形，同时能在12864上显示波形类型和频率，用FPGA verilog实现的-DDS direct digital frequency synthesizer can produce sine, square wave, sawtooth wave, triangle wave four waveform, while in the 12864 on display the waveform type and frequency
BVerilog_examo
- 关于FPGA的书籍，介绍了大量的Verilog实例例，对初学者很有帮助 ，经测试可直接使用。 -FPGA book introduces the Verilog instance cases, useful for beginners, has been tested and can be used directly.