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1_lab1
- （1）熟悉S6 CARD实验板； （2）熟悉ISE集成开发环境； （3）3比特加法器仿真与上板实验； （4）m序列产生器仿真与在板Chipscope调试 -(1) be familiar with the S6 CARD experimental board (2) be familiar with ISE Integrated Development Environment (3) 3-bit adder simulation experiment on board (4
ChipScope_use
- xilinx chipscope的实用教程，步骤有图，一步步学习，简单实用-Xilinx chipscope practical tutorial, step diagram, a step-by-step learning simple and practical
Lab05-Chipscope_Debugging_13_1_1
- xilinx fpga microblaze Embedded Chipscope DebuggingThis is the fifth tutorial in a series of training material dedicated to introducing engineers to creating their first embedded designs. These tutorials will cover all the required steps for creating
LED
- xilinx V6板卡上的根据时钟的LED流水灯程序，包括chipscope的时序提取模块，已在在V6上验证通过-xilinx V6 under the clock on the board LED light water procedures, including the timing chipscope extraction module has been verified through on the V6
DDR2_Control
- 本文档以Siga-S16 Spartan 6的FPGA开发板为例，为大家介绍用MIG工具生成DDR2控制器，并用ChipScope调试DDR2读写的方法。 -This document in the FPGA development board Siga-S16 Spartan 6 as an example, to introduce the formation of DDR2 controller with the MIG tool, and use the debug method of
fpga_UART
- 在ISE virtex6 开发板上测试成功的串口收发程序 可用chipscope查看数据 并且包含仿真测试程序-In ISE virtex6 development board test successful serial transceiver can be used to view the data and contains chipscope simulation test program
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
aurora_bram
- Xilinx SP605评估板 Aurora IP(GTP 简单协议) 核功能验证 调试源代码 chipscope验证通过-Xilinx SP605 Evaluation Kit Aurora IP core functional verification debugging source code and chipscope verified
AD6643_test
- verilog实现AD6643芯片的驱动，用200MHz采样率对A、B两路信号进行采样，可以在chipscope中观察到A路和B路的数字信号，已验证程序正确可用。-Implemented in verilog language AD6643 chip driver with 200MHz sampling rate of A, B two-way signals are sampled can be observed A and B road in chipscope digital signa
ultrasonic-ranging
- 完整的xilinx工程，基于Chipscope的超声波测距调试,每秒产生1个超声波测距模块所需的10us高脉冲激励，并用 chipscope pro查看回响信号-Based Chipscope Ultrasonic Ranging Complete xilinx project，debugging, generating high per 10us pulse required an ultrasonic ranging module incentives and view echo sig
sp6_SRAM
- SRAM读写测试实例，每秒钟进行一次单字节的SRAM 读和写操作，用chipscope查看时序波形。 -SRAM read and write test cases, once per second single-byte SRAM read and write operations, with chipscope view waveforms.
Verilog HDL program
- 文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and
sp6ex15
- SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)
RS
- 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS
SRAM
- SRAM读写测试实例，每秒钟进行一次单字节的SRAM 读和写操作，用chipscope查看时序波形。(SRAM read and write test instances, each time a single byte SRAM Read and write operations, use chipscope to see the timing waveform.)
ezidebug-code
- Ezidebug 支持Xilinx，chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)
BPSK
- 先用Matlab理论仿真，得出滤波器系数。再用Verilog语言在ISE环境下编写程序，通过Modelsim和ChipScope进行波形仿真和引号抓取，从而提高调试的效率。通过手机发送指令来控制上下变频器的参数。(Firstly, the filter coefficients are obtained by simulation with the theory of matlab. Then the program is written in Verilog language under IS