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digital_seven_segment_clock
- digital seven segment clock
clocktest.vhdl
- 时钟测试，vhdl，四位状态灯的转换，有复位信号-Clock test, vhdl, four status lights conversion, there are reset signal
digitalclock
- 数字电子钟，24时制计时，带有调时功能，对分秒时分别进行调整。-Digital electronic clock, 24 when the system time with when the transfer function, minutes and seconds, respectively to adjust.
lab8
- 此實驗中我們將量 測人的反應時間，由於人的反應時間遠比起內建CLOCK的週 期長的多，因此要對CLOCK做除頻的動作方可適用，並方便 於計數 器的計算與 七段顯示器的呈現。實驗內容為，當看到LED亮 起時，立 即做出反應將計數 器停 下，並顯示出當時計數 器之時間。計數 器以兩 位數 BCD counter來 實現並將結果 顯示於七段顯示器上。-Vo
digitalwatch
- Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The e
e7v4
- 数字钟：显示，设置时间，设置闹铃（报时），秒表。 平台：quartusII 5.1。 说明：此版本中已将系统时钟调快，自己稍微改动一下即可，小小的考验，做出来会更有成就感！-digital clock：display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want th
SZZ
- 这是一个数字钟的VHDL语言，具有调时、调秒、调分功能，同时，还具有十二小时制向二十四小时制切换功能-This is a digital clock in VHDL language, with a tune, the tone seconds and sub-transfer function, while the system also has 12 hours to 24 hours the system switching function
clock
- 基于vhdl的数字钟,分别由6个数码管显示24小时、60分钟、60秒的计数显示；设有校时、校分、秒清零校正功能，分别由3个按键控制；验证可用。-On vhdl digital clock, respectively, by 6 digital tube display 24 hours, 60 minutes, 60 seconds of the count display with school hours, school hours, seconds, cleared correction
vhd_design
- 我学习VHDL的课程设计，是多功能数字钟，有闹钟，秒表等功能，多指教-I learned VHDL course design is multi-functional digital clock, there is an alarm clock, stopwatch functions, multi-Zhi Jiao
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
wtut_edif
- Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
clock
- 用VHDL写的带有小时，分钟，秒的电子钟，已在FPGA开发板上调试运行过，显示very well!-Written in VHDL, with the hours, minutes, seconds, the electronic clock has been running in the FPGA development board debugger before, show very well!
Digital6Counter
- 多功能数字时钟 功能齐全 vhdl fp-Multi-functional digital clock vhdl fpaa
clock2Hz
- this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga.
8051alarmclock
- A complete collection of a simple alarm clock with minimum compenents used and simulation in proteus The hardware is complete and practically implemented with 100 success.-A complete collection of a simple alarm clock with minimum compenents used a
clock
- a vhdl code for digital clock
ds32c35
- ds32c35是dalas生产的实时时钟（RTC）芯片，本程序（在EP2C8Q208C8N上调试通过）在FPGA上构建I2C接口于此时钟芯片通信。可以在LED上动态实时显示时间。利用本程序也可以改编成高精度实时时间测量的程序-ds32c35 is produced by dalas real-time clock (RTC) chip, this program (in the EP2C8Q208C8N debugging via) in the FPGA built this clock ch
eetop.cn_digital_clock
- 基于VHDL的数字时钟设计课件，简单，实用-VHDL-based Digital Clock Design Courseware
clock
- 基于VHDL的电子时钟，模块少，连线简单，具有简单的调整时和分的功能。-VHDL-based electronic clock, the module small, to connect simple, with a simple adjustment and sub-functions.