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yiweijicunqi
- 使用并置“&”法写出通用移位寄存器的VHDL模型。在时钟控制下将输入数据寄存，在满足输出条件时输出数据。-Use and set & method common shift register to write VHDL models. Under clock control the input data registers, the output data in the output condition is satisfied.
DD
- This file is the VHDL code for controlling the stepping motor. The clock driving the stepping motor driver module. through signal it can control the direction of the stepping motor.-This file is the VHDL code for controlling the stepping motor. The c
cntr_4bit
- This the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit-This is the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit
clockdiv
- Clock division implementation on verilog VHDL
i2cBUS
- Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source
ELECTRONICCLOCK
- VHDL语言设计的电子钟，并且有暂停功能和清零功能的按键实现，并且带秒表-VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
ClockQUARTUSVHDL
- 12/24小时数字时钟VHDL设计 包括顶层文件的设计和VHDL源程序-12/24 hour digital clock design, including the top-level VHDL design and VHDL source code file
example7_jtd
- VHDL实现交通灯，通过分频操作实现对灯的控制和延时，运用的多种分频时钟来控制进程。-VHDL to achieve traffic lights, through the frequency control and the frequency of the lamp control and delay, the use of a variety of frequency control clock to control the process.
shuzizhong3
- 数字钟VHDL软件设计，包含多种功能，报时，12,24切换，调时-The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable
Control_AD9516
- 时钟芯片AD9516配置代码，VHDL开发，可仿真验证-Development, clock chip AD9516 configuration code, VHDL simulation
Fibonacci
- （1） clkdiv 模块：对50MHz 系统时钟 进行分频，分别得到190Hz，3Hz 信号。190Hz 信号用于动态扫描模块位选信号，3Hz 信号用于fib 模块。 （2） fib 模块：依据实验原理所述Fibonacci 数列原理，用VHDL 语言实现数列 （3） binbcd14：实现二进制码到BCD 码的转换，用于数码管显示。 （4） x7segbc：采用动态扫描，使用4 位数码管依次显示Fibonacci 数列数据。 实验采用3Hz 频率来产生Fibonacci
count
- 本实验利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发 时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数。 SW0 为复位开关。当开关拨至高点平时，计数器归0，当开关拨至低电平时，计数器开始计数。 该电路包括分频电路，计数器电路，二进制转BCD 码电路和数码管显示电路。-This experiment uses VHDL hardware descr iption language to design a 0 ~
FPGA_exp2
- 调节数码管显示的文件，适用于CYCLONE II 开发板， 用VHDL语言编写，非常适合移植进数字钟中以实现调节时间的功能。 多模块设计简单明了。-Adjust digital display files for CYCLONE II development board, using VHDL language, it is very suitable for transplantation into digital clock to realize the function of regula
code
- vhdl code which includes various codes of clock divider uart lcd etc
Eclock
- Xilinx实现电子时钟功能，具有调整时间功能，设置闹钟功能，闹钟播放音乐等，非常适合VHDL入门。-Xilinx implement electronic clock function, have adjustment time function, set the alarm function, the alarm to play music, ideal for entry VHDL.
visualitzador7segments-20170516T144823Z-001
- Code in VHDL of a segments visualizer (used for a clock)
contador_v4-20170516T144731Z-001
- VHDL for a counter used in a clock.
counter (2)
- This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3