搜索资源列表
PLL
- SOPC 系统集成编译的PLL IP核 Verilog代码-pll ip core in SOPC
HW
- 关于 Altera DE2开发板上面的资料。各个控制模块的核心类容都在里面，采用Verilog 编写。-About Altera DE2 development board above information. Each control module is the core content classes are on the inside, written using Verilog.
USB_Core
- USB Core in Verilog for implementation into FPGA devices.
pwm
- Verilog 语言开发的PWＭ IP软核 验证实现了PWM 输出-Verilog language development of PWM IP verified to achieve a soft-core PWM output
softdrink
- 饮料自动投币售卖机核心控制电路，功能包括开始操作，取消操作，找零，用Verilog实现-Automatic beverage vending machines coin core control circuit functions include start operation, cancel the operation, give change, achieved using Verilog
dcm_IP
- 这是一个用verilog语言编写的程序，利用了自带的DCM IP核，可以做练习用-This is a program written in verilog using a built-in DCM IP core, you can do the exercises with...
SPI
- Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous comm
IFFT11111
- 使用Verilog编写的IFFT，ISE12.2下编译通过，学习IFFT核的同学可以参考-Use of the IFFT in Verilog compiler, ISE12.2 under study IFFT core students can refer to
timer_ip_core
- timer ip core 8 bit, verilog simulation and coding
can_verilog_IP.tar
- 运用Verilog语言编写的CAN控制IP核，符合CAN2.0B协议，仅作为参考！-CAN controller IP core using Verilog language, in line with CAN2.0B agreement, only as a reference!
VGA_CCD531
- 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的
EEthhernet_vet
- Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核，对学习verilog语言与以太网有非常大帮助。 -Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet.
9b93752447d7
- 用verilog 写的 USB 驱动 适用于SOPC IP CORE-USB drive write verilog. For in the SOPC IP CORE
openfire2_latest[1].tar
- VGA 到LVCD verilog 源码，接口为RGB4:2:2 模式可以选择-The OpenCores Enhanced VGA/LCD Controller Core provides VGA capabilities for embedded systems. It supports both CRT and LCD displays with user programmable resolutions and video timings, thus provid
viterb_encoder_and_decoder_latest.tar
- Category: Arithmetic core Language: Verilog Development status: Mature Additional info: Design done, Specification done WishBone Compliant: No
minicpu(compiler-8bit)
- CISC microprocessor IP core & 8 bit compiler, verilog语言编写，可在FPGA和CPLD上综合实现,结构类似Intel 8085-CISC microprocessor IP core and 8-bit compiler, verilog language, FPGA and CPLD comprehensive realization .structure is similar to Intel 8085
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
divider
- VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
SAR_Send
- 对altera的RS编解码IP核进行仿真，并且写了编解码的控制模块，用verilog实现，通过仿真，编码和解码功能正确。-test of RS code and RS decode,by using quartus ii9.0 with the IP core