搜索资源列表
fft_test
- ALTERA的FFT IP核时序的仿真，verilog语言。采用burst方式，FFT点数2048点-FFT IP core of timing simulation ALTERA, verilog language. Using burst mode, FFT points 2048 points
sd_controller.v
- SD卡的IP核，Verilog代码编写，与MCU挂载后实现SD卡的读写数据。-SD card IP core,programmed by verilog,link to MCU can R/W data to the SD card.
t4_fifo
- FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want to be useful.
can_latest.tar
- 基于Verilog的CAN控制器的IP核，可以参考-The CAN controller IP core based on Verilog
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code
spdif_verilog
- 数字音频接口spdif ip core，verilog语言编写，带有testbench-spdif verilog ip core
RAM_InterWave
- RAM 通过ip核的生成使用verilog 的编写的，可以拿来直接进行例化使用。-RAM generated by using verilog ip core prepared, can be used directly instantiated using.
verilog_cordic_core
- A highly configurable 1st quadrant CORDIC core in verilog-Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other projec
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
FIR
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
I2C_Single_Master
- I2C Single master written in Verilog Libero Designer core generator.-I2C Single master written in Verilog Libero Designer core generator.
reed_solomon_decoder
- Reed Solomon Decoder written in Verilog Libero core generator.-Reed Solomon Decoder written in Verilog Libero core generator.
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.
RX_ASYNC_for_module_UART
- Rx Async for module UART written in Verilog Libero Designer core generator.-Rx Async for module UART written in Verilog Libero Designer core generator.
TX_ASYNC_for_module_UART
- Tx Async fpr module UART written in Verilog Libero core generator.-Tx Async fpr module UART written in Verilog Libero core generator.
SPI_Core_2
- 用Verilog HDL 语言编写的，可在FPGA上实现的SPI总线主端 收发读写模块 -SPI Master Read-Write controller core which was Writted by Verilog HDL based on fpga
DES_Triple-DES-IP-Cores
- Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
IPcore
- verilog IP核调用子程序，源码-Verilog IP core call subroutine, the source code
switch_fabric
- verilog 写的具有代数交换功能的数据交换，是交换机设计的核心部分。-Switches Core by Applying Algebraic Switching
IIC
- 这是一个关于verilog的IIC内核，已经经过验证，没问题-this ia a core for IIC of verilog .It is OK for runing.