搜索资源列表
i2c_master
- I2C master模式的IP core（verilog）-I2C master mode IP core (verilog)
IP-coreincluding-VHDL-and-Verilog
- 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
LCD_1602_Interface_IP
- verilog 写的LCD1602 IP核-the LCD1602 IP core verilog write. . . .
verilog-ip-core
- verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
8051core-Verilog
- 用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！-Verilog FPGA internal 8051 core, super, super hard to find! Shared out!
ARM-Verilog-HDL-IP-CORE
- ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
verilog
- it is xilinx SDR SDRAM controller core
8051core-Verilog
- Verilog实现8051 core.基本可用，基于Altera硬件平台实际验证通过。-how to implement 8051 core via verilog.
CORE-8051
- 8051核的VERILOG实现，适合于学习，包括模块程序，测试程序和说明文档。-The 8051 nuclear Verilog achieved suitable for learning, including the module procedures, test procedures, and documentation.
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
8051based_on_Verilog
- 8051的内核的verilog实现,有完整源代码，部分注释-8051 core verilog achieve
cordic
- Altera 的CORDIC IP核，Verilog HDL-Altera CORDIC IP core, Verilog HDL
fpga-jpeg-Verilog
- jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
8051core-Verilog
- 基于Verilog的 8051 IP核 内含 Testbench-The 8051 IP core based on Verilog
aes
- AES的IP核,AES的加密解密算法，包括密钥扩展程序-aes core verilog
color-correction-using-verilog
- FPGA Implementation of Color Correction Core using Verilog
rtl_1795
- Developper:mathswork Arm IP Core Verilog This IP core is an ARM clone. It has the same architecture of ARM v4. Its main feature lists: Not support coprocessor instructions Not support THUMB instruction set All interrupts
FPGA-Prototyping-By-Verilog-Examples
- HDL (hardware descr iption language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical impl