搜索资源列表
VHDL-counter-code
- 用WHDL实现计数器的各个模块设计，并用FPGA进行功能验证！-With WHDL counter module design and functional verification using FPGA!
counter
- vhdl语言做的4位可逆计数器和格雷码转换器，包括具体代码和仿真结果-vhdl language do four reversible counter and Gray code converter, including a specific code and simulation results
binary_counter_timer_64
- vhdl code which implement a six binary counter, with adjustable frequency.this module is tested in Quartus tool of ALTERA.
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
4-bit-Ripple-Carry-adder
- it is 4 bit ripple carry adder. it is one type of counter you can say. in which carry is added. it is vhdl code and its waveform which is run in altera quars II.
seconds-counter
- 在EP2C5T144C8开发板上编的一个VHDL源程序，相当于一个秒表，读数可在4个数码管上显示，通过按键可暂停计数，可继续计数-In EP2C5T144C8 development board this a VHDL source code, the equivalent of a stopwatch, reading on the four digital tube display, can suspend count by buttons, can continue to count
code
- 这是一个关于vhdl中counter程序 很简单 但是在数据控制系统课程实验中很常见的counter编程-This is a very simple procedure vhdl the counter but in the experimental data control systems course very common counter programming
Counter
- 用VHDL设计具有清除端、使能端，计数范围为0-999的计数器设计。输出为8421BCD码-VHDL design with a clear end to enable the end, the design for the counter counting range 0-999. 8421BCD code output
johncounter_D
- VHDL CODE FOR JOHNSON COUNTER USING D FLIPFLOP
syncup_dn
- VHDL CODE FOR SYNCHRONOUS UP/DOWN COUNTER
60_binary_counter_vhdl_quartus2
- 一个60进制的计数器的VHDL源代码，测试可行。-a VHDL code of 60 binary counter and it test feasible.
gray_binary_conv
- 用VHDL实现的格雷码，有格雷码计数器、格雷码转二进制、二进制转格雷码！-VHDL implementation of the Gray code, there is Gray code counter, Gray code to binary, Gray code Binary!
code
- 设计一个同步二十四进制计数器，理解触发器同步计数工作机制，掌握同步触 发控制的VHDL描述方法以及异步清零的描述方法。 -Design a synchronous binary counter twenty-four understanding count the trigger synchronization mechanism, master synchronous trigger VHDL descr iption method and asynchronous clear desc
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
hex7segb
- Implimentation of the switches and 7 segment display bit counter on an Altera DE2 baord via VHDL code on the Cyclone II FPGA
chirp
- VHDL CODE Of chirp counter
SOC_Code
- 加法器，原码补码乘法器，ROM设计，PC计数器等的VHDL详细代码-The source-code complement adder, multiplier, ROM design, such as PC counter of VHDL code in detail
bitcounter
- one bit up counter using VHDL code -one bit up counter using VHDL code
Compteur_VHDL
- VHDL code of a counter Code VHDL d un compteur
Register
- this code is by VHDL language for register ent counter register and