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counter_4bit_code
- vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares-vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares....
branches
- vlsi counter code uploaded in vhdl language
shierjinzhi
- 十二进制计数器应用VHDL源代码编写的，程序易懂-Ten binary counter applications written in VHDL source code, the program easy to understand
jishuqi
- 带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。用VHDL源代码描述-With count enable, asynchronous reset, brought by a six-bit output of the binary counter, counting the results from the common cathode seven segment LED display. Described with the VHDL source co
count
- 1．用VHDL设计具有清除端、使能端，计数范围为0~999的计数器，输出为8421BCD码； 2．用VHDL设计十进制计数器（BCD_CNT）模块、七段显示译码器电路（BEC_LED）模块和分时总线切换电路（SCAN）模块。 3．用MAX+plusⅡ进行时序仿真。 -1. VHDL design with a clear end to end so that the count range of 0 to 999 in the counter, the output is 8421B
conter
- code of a counter with vhdl very hey descr iption language it counts from 0 to 255
kbm
- 基于VHDL硬件描述语言的可变模计数器的仿真案例代码及操作步骤-VHDL hardware descr iption language based on the variable-mode counter case simulation code and the steps
Counter24hour
- 用VHDL语言编写的一个二十四进制计数器，一个脉冲输入引脚，一个复位输入端，四个BCD码输出端。与我另外的八个模块是配配套的。-A 24 binary counter programmed with VHDL language.A pulse input, a reset input, four output BCD code. It is one of my total 9 modules that are used to design a digital clock.
Counter60sec
- VHDL语言编写的一个六十进制计数器(用于秒)，一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。 -A 60 binary counter（for second） programmed with VHDL language.A pulse input, a reset input, eight BCD code output. It is one of my total 9 modules that are used to de
prjadd
- vhdl计数器，在quartus81下调试通过-vhdl counter code. the code is passed with quartus81
week_9
- vhdl程序实现了计数器的 是一次作业的源代码-VHDL program counter is a one-source code
count_9
- this code vhdl of an binary counter with adjustable frequency
contador
- this is a code for vhdl, is a counter 0 to 99 with clock
Nouveau-Document-texte
- sources code on VHDL to descipe a counter architecture
74LS160jishuqi
- 74ls160十进制可预置计数器VHDL语言代码-74ls160 decimal VHDL language code can be preset counter
counter_
- VHDL源代码+工程，可改变时钟的计数器-VHDL source code+ project, can change the clock counter
cnt60
- 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.
cnt2
- 16位二进制计数器及设计代码其测试代码（vhdl）-16-bit binary counter and design codes and test code (vhdl)
count
- 本实验利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发 时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数。 SW0 为复位开关。当开关拨至高点平时，计数器归0，当开关拨至低电平时，计数器开始计数。 该电路包括分频电路，计数器电路，二进制转BCD 码电路和数码管显示电路。-This experiment uses VHDL hardware descr iption language to design a 0 ~