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27899801
- programming CPLD and FPGA Code
Dcufaqi
- hdlthis is a FPGA and cpld good this a FPGA and cpld good-this is a FPGA and cpld goodthis is a FPGA and cpld goodthis is a FPGA and cpld good this is a FPGA and cpld good this is a FPGA and cpld good
FPGA_Designdiscrinple
- FPGA/CPLD 数字电路设计经验分享，来源别人的经验和设计技巧。-FPGA/CPLD digital circuit design experience to share, the source of experience and design skills of others.
FPGA_CPLD
- FPGA/CPLD数字电路设计经验分享,内容包括数字电路设计的一些经验。-Sharing the experience of designing digital circuit with FPGA/CPLD
shouchishiboqi
- 手持式存储示波表中的数据采集设计。以ARM和单片机为主辅，FPGA/CPLD为逻辑平台-Handheld storage oscilloscope table data acquisition design. ARM-based microcontroller and secondary, FPGA/CPLD logic platform
FPGACPLD
- fpgA和cpld的概述及芯片内部结构介绍。-fpgA and cpld overview and introduce the internal structure of the chip.
sin_10M
- FPGA/cpld 产生步进为1Hz的正弦波,最大为10M,使用的晶振为50M -FPGA/cpld generation step of 1Hz sine wave, up to 10M, 50M crystal oscillator for use
IntroductionPtoPCPLDPandPFPGAPDesign
- Introduction to CPLD and FPGA Design
Altera
- VHDL verilog fpga cpld-DIGITAL
ALTERA_CPLD_and_FPGA_device08_09_27-
- 第4章ALTERA的CPLD与FPGA器件08_09_27嵌入式编程系列-Chapter 4 ALTERA CPLD and FPGA devices in embedded programming series 08_09_27
Frequency-counter
- 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (fi
debounce_1_Sch
- 用QuartusII原理图形式编写的按键消抖程序,分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下的时间与产生低电平信号的时间相等,按键按下的时间与LED灯亮的时间相等-*Project Name :debounce_Sch *Module Name :debounce_Sch *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *D
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
PWM_modem
- 8bit PWM encoder and decoder, the zip includes PWM timing and both decoding and encoding modules. The system will run perfectly on any CPLD or FPGA. Documentation regarding the design is also included.
PseudoHC11_MCU
- This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an
Reflex
- This simple program tests the reflex of a person. It will randomly start a timer and after some seconds the person will be told to press a certain button. The CPLD or FPGA will know with a resolution of 1mS the time elapsed time between the command a
qiduanxianshiyima
- 利用译码程序在FPGA/CPLD中实现16进制数的译码显示.通过EDA原理图设计方法利用prim库中7448芯片进行7段译码显示-Using decode program FPGA/CPLD realized in hexadecimal number decoding display. Through the EDA principle diagram design method using the prim library 7448 chips for 7 period of decodin
CRC
- 在CPLD 或者ＦＰＧＡ中实现CRC,可以查找表方式或根据原理去实现-CPLD or FPGA CRC can lookup table according to the principle
newdecode
- 密码锁，大学数字eda课程顺序锁的源代码，有2位或者4位的顺序锁，可以在fpga或者cpld上实现 -Password lock, digital eda course the order of the source code of the locks, the order of two or four locks, and can be implemented on the fpga or cpld
num09211870
- 北邮大学VHDL课程的结课题代码，一种基于fpga或者cpld实现的拔河机器代码-BUPT Results of VHDL course subject code, based on fpga or cpld tug of war machine code