搜索资源列表
MIPS_CPU_OR2000
- MIPS架构的开发的CPU软核OR2000 verilog实现，MIPS体系结构cpu设计入门参考-The development of the MIPS architecture CPU soft core OR2000
SystenInfor
- 可以显示系统信息，如硬盘，cpu，mac等等，不错-Can display system information, such as hard disk, cpu, mac, etc., well
s5pv310--CPU-Board-a-Main-Board-
- cortex A8 S5PV210 设计参考原理图，PDF文档-cortex A8 S5PV210 reference design schematics, PDF documents
FPGA-and-cpu
- FPGA与单片机的串行通信接口的程序设计-FPGA and cpu
soc
- 精简的单周期CPU设计代码，适合SOC设计初学者,基本模块包括LED，switch bar，seven segment-Streamlined single-cycle CPU design code for SOC design for beginners, basic modules include
RISC_CPU
- 一个简单CPU设计，可以让读者在计算机组成原理和verilog语言方面受益-A simple CPU design, allows the reader to the computer principles and Verilog language benefit
CPU
- CPU控制部分采用微程序设计方式，可是实现简单的加减乘运算-CPU control part of the micro-programming mode, but the simple addition and subtraction, multiplication
cpu
- 用FPGA实现了CPU中RAM,ROM等功能，设计比较完整-FPGA Implementation of a CPU, RAM, ROM, function, design is more complete
singlePcyclePMIPS2
- 多周期MIPS实现的CPU设计方案，包括源码-MIPS multi-cycle
Single-CPU-clock-cycle-
- 单时钟周期CPU的设计实验，能完成16条基本指令。-Single CPU clock cycle of experimental design，Article 16 to complete basic instructions。
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
CPU-project
- 硬件实验 设计一个给定指令系统的处理器 支持多条指令带进位和不带进位的ADD，SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,清零等等，内有设计报告-Hardware experiment，design a CPU with the command following:SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,clear, and so on.There is a disigning report in it.
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
CPU
- 东南大学COA下实验设计CPU完整程序，可以在RAM中写程序并可观察各个输出的波形，用于检验。-south-east university COA II the design cpu lesson which you can write your own program in the cpu and also can chack the wave
lab05_09122011
- 多周期CPU设计，可以实现22条基本指令。实现简单，包含实验报告-CPU design
lab06
- 流水线CPU设计，最接近真实运行的学生实验课的CPU设计，是组成原理实验课大作业，包涵详细讲解-CPU design
8_RISC_CPU
- risc-cpu，简单的cpu设计,强大的功能简洁的设计，精简化-verilog risc_cpu
yuanma
- MIPS指令源代码，用于CPU设计，计算机组成原理课设所需要的源代码下载-MIPS instruction source code for the CPU design, computer composition principle lesson to set the source code download
16-bit-CPU
- 单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书-Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions
TVerriRiscCPPh
- 这个文件中使用verilog hdl简单易懂懂的运用基本运算实现了微型的cpu设计开发过程 -Verilog hdl straightforward to understand the use of basic operations miniature cpu design and development process used in this document