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51Developer
- 1602和24C02芯片一起编写时钟发生器程序，1602主要用于显示，2402用于随时储存数据， 使得断电后数据能够保存 上电后能继续走动-1602 and 24C02 chip clock generator with the writing process, mainly for 1602 show that 2402 is used to store data at any time, so the data can be saved after power off after pow
wannianli
- 1602和24C02芯片一起编写万年历（每个月的天数完全按照真实黄历而来） 发生器程序，1602主要用于显示，2402用于随时储存数据， 使得断电后数据能够保存 上电后能继续走动-1602 and 24C02 chips prepared with the calendar (the number of days each month in full accordance with the real almanac from) generator program, 1602 is mai
1730
- 波形发生器的使用和产生波形的主要原理的进行分析与数据处理-Waveform generator produces waveforms used and the main principles of analysis and data processing
cloud
- 云发生器 能方便的把数据聚类 在matlab上实现，很方便。-Generator can easily cloud the data clustering in matlab to achieve, it is convenient.
AD9850_1_V3_C
- 函数信号发生器9851资料，有程序开发。产生信号最大有40MHZ。-Function Generator 9851 data, there are program development. Produce the maximum signal has 40MHZ.
awg
- 基于FPGA的任意波形发生器源代码，并且添加了上位机发送指令和数据（低八位用来发频率控制字，高八位用来发指令）。-FPGA-based arbitrary waveform generator source code, and add the host computer to send commands and data (low eight frequency control word is used to send high eight used to send commands).
CRC3.0
- 此代码的功能是实现网络纠错当中的循环冗余码纠错法，即输入一个初使二进制比特流与生成多项式可以得出一个拥有循环冗余纠错码的二进制比特流，此比特流如果转输到目的地就可以进行差错验证了，以保证代码的正确传输。代码注释里有详细的测试数据与说明。-This code is a network error-correcting function among the cyclic redundancy code error correction method, that is early to make a
xinhao
- 基于DDS技术多功能信号发生器，拥户可通过键盘输入所需频率信号的数据，利用单片机STC89C52传送出相应的频率控制字，并对DDS芯片AD9833进行编程，幅度的调节由可调电位器实现，最终得到所要求的输出波形- Multifunctional signal generator，In this system user can input the frequency data through a keyboard, and the microcontroller STC89C52 will tran
TMG_6.0R7
- matlab text matrice generator tool for math representation of textual data
Harmonic-Wavelet-Analysis
- 首先给出了谐波小波时频剖面图检测含噪声信号的微弱奇异成分的方法 然后运用谐波小波时频剖面图方 法分析了碰摩故障仿真信号 最后利用该方法对多个实际汽轮机组动静碰摩故障的真实振动信号进行了分析研 究。结果表明, 谐波小波能够得到其它信号分析方法无法得到的特征, 有效识别机组的碰摩故障。-Harmonic wavelet time frequency profile plot is introduced firstly in practice to identify weak
Cosgrove-Software-Model-Zip-Folder
- The is a fully functional GPS SDR. It can accept real data or simulate its own data. It performs correlation, signal parameters discrimination, and loop filtering both code and carrier with the option of carrier loop aiding of the code loop. There ar
Spread1
- 对输入的数据采用BPSK 调制方式后转为ASCII格式，采用混沌方法去传输二进制序列。 -The input data into ASCII format using BPSK modulation, chaotic way to transfer binary sequence. There are different chaotic sequence generator...
cekongxitong
- 一个虚拟测控系统，可以采集信号发生器里的信号并对其进行处理（频率计算与fft变化等），可提取数据与保存数据-A virtual control system, can acquire the signal generator signal and its processing (frequency calculations with fft changes, etc.) can extract data and save data
dianziyindiaofashengqi
- 这次实验是电子音调发生器，首先我们要了解发声的原理，节拍和频率的关系。所有音乐都是由各个不同频率的音阶和其延续时间的长短来实现的。不同的音乐是由不同的音阶按某种排列播放一定的时间而形成的。将各音阶和其延续时间分别存放在数据段中，然后根据不同的按键选择不同的音阶和时间表，在用计数器产生该音阶频率，然后通过蜂鸣器发音。-This experiment is the electronic tone generator, we need to understand the principle, rhyt
poisson_gen-1.2
- poison generator is a tools to generate a random data for network simulation ns-2.-poison generator is a tools to generate a random data for network simulation ns-2.
eda
- EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时
xueshengguanli
- [1]注册模块 [2]成绩管理模块 [3]选课、重修模块 [4]学籍、班级管理模块 [5]考勤模块 [6]奖惩模块 [7]文件传输共享作业资料模块 [8]留言帮助模块 [9]数据处理(批量导入、各种文件格式导出、报表生成、预览打印)模块 [10]系统日志模块-[1] The registration module [2] performance management module [3] Course, rebuilt module [4] enr
Based-on-SPCE061A-counter
- 计数器基于凌阳SPCE061A微处理器设计,对高频信号采用测频法,提高精度,对低频信号采用测周法,可最大限度减小误差。能够接收函数信号发生器产生的信号,实现周期测量和时间间隔测量。可记忆10个测量的历史数据,实现语音报数功能且能够显示温度等多种功能。本系统经实验调试,较好地实现了预定的功能,由于采用了凌阳单片机控制,系统可靠性和性价比较高。- The designed counter adopts Sunplus SPCE061A MCU,uses frequency measurement f
Proj_final
- The project is conducted in the assembly of an RC low-pass filter on a board and breadboard implementation of a program in LabView it possible to obtain filter characteristics. To this end, it is necessary GPIB control through the function generato
RISC_CPU
- VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator,