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FPGA_fenpin
- 利用FPGA构建一个1:1的分频器，稍加修改即可改成频率可控获占空比可控的时钟输出。-Using FPGA to build a 1:1 divider, you can change the frequency slightly modified controllable duty cycle controlled by the clock output.
fenpin
- 分频器的实现将不同频段的声音信号区分开来，分别给于放大，然后送到相应频段的扬声器中再进行重放-FDCT Frequency Divider
8fen
- 8分频器的VHDL源码，绝对正确，并且可根据本代码推导出各个2的幂数的分频器的编写原理。-FDCT Frequency Divider by VHDL .
diver
- 利用VHDL语言设计了五位除法器 实验环境为maxplusII 内有各个模块详细的程序代码 以及相应的模块截图-Designed using VHDL, five divider within the experimental environment maxplusII detailed code of each module and the corresponding module screenshot
fenpin
- 时钟分频器，初学者可以下载学习，效果比较好-Clock divider, beginners can download the study results were quite good
81404600N_counter_VHDL
- 分频器一个n分频器的源代码任意N进制计数器标准代码写法-Divider divider of the source code of a n N binary counter any standard code written
ca60
- 60分频器，将主频分频，产生系统所需信号。-60 divider, the frequency divider to generate the necessary signal system.
xiyiji
- 洗衣机控制程序，包括分频器，计数器，触发控制器等。-Washing machine control procedures, including the divider, counter, trigger controller.
dividerwithsignal
- 本程序是用verilog实现带符号的二进制除法器。本代码可用。-to realize the divider
dividerwithoutsignal
- 本程序是实现8位无符号的除法器，得到的结果有商和余数，分别放在两个寄存器变量里面。-divider withoutsignal
power_divider_based_ADS_simulation
- 这是一个基于ADS的功分器制作的PPT，从理论到实践仿真，比较全面，以供参考。-power divider based ADS simulation.
fpga_chufaqi
- 基于fpga的32位除法器的设计，开发环境vhdl-Fpga-based 32-bit divider design, development environment vhdl
COUNT
- 设计一个最大分频为225的分频器，将50MHz时钟作为输入。分频器可以通过计数器来实现，通过一个25位的计数器，然后在最后一位输出，则产生了一个最大分频为225的分频器。-Design a maximum frequency divider 225, the 50MHz clock as input. Divider can be achieved through the counter, through a 25-bit counter, and then the last one out,
0101
- Quartus II 除法器，用VHDL语言编写的.除法器。-Divider using VHDL language. Divider
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
EDA2
- 学习数控分频器的设计、分析和测试方法。数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC crossover study design, analysis and testing methods. NC divider function is that when the input given different input data, input th
div_fru
- 介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。-Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not
frenquent
- 分频器的一些程序。包括整数分频，小数分频，我感觉非常好的资料，不敢私自分享。特拿出来分享。希望想学习的好好参考下，肯定会有所感悟。-Divider of some procedures. Including the integer frequency, fractional, and I feel very good information, not privately share. Point out to share. They want to study more carefully th
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
wave
- 这里面是关于微波技术的一些试验程序，和仿真模型，主要有微带线，带状线，功率分配器，支节匹配器-This is on microwave technology, which some experimental procedures, and simulation models, mainly microstrip, stripline, power divider, branch of the matcher