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fenpinqi
- 分频器的一个例子，有源代码的，希望给大家带来帮助-Divider' s an example of source code, and I hope to give us help
lowpower_dynamic_clock_divide
- Low power dynamic clock divider
div32
- 基于verilog的分频器 23分频器 可更具需要修改成任意偶数分频器-23 divider verilog-based crossover can be even more need to modify the divider into any
clk_div_n
- 时钟任意分频模块，输入为主时钟和分频数，输出为主时钟/分频数。-Clock divider
jiaocuofenpin
- 用硬件语言写了一个由8/9分频构成的无限不循环小数分频器，分频系数k=260/31-Written language with the hardware a 8/9 frequency divider consisting of an infinite non-recurring decimal, frequency factor k = 260/31
traffic
- 采用VHDL语言编写的控制交通灯工作的程序。分为四个部分：1，分频器，2，计数并产生控制信号，3，交通灯信号产生，4，交通灯总体描述。点击lzh6.aws打开工作空间-VHDL language used to control traffic lights work procedures. Divided into four parts: 1, divider, 2, count and generates control signals, 3, traffic signal generatio
VHDL
- 除法器 4位除法器 可以编程实现 有启发意义-4-bit divider divider can be programmed instructive
verilog_std_div
- Verilog HDL语言实现任意整数分频.只需调节分频数和分频位宽即可。-Verilog HDL language to any integer divider. Simply adjust the number and frequency can be frequency division-bit wide.
VHDL_fre_div
- 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of ex
sprc196
- 無傳感器控制的三相無刷直流電機（無刷直流）馬達使用梯形減刑計劃與反電動勢（反電動勢）測量獲得通過簡單的電阻分壓器。閉環電流控制採用 PID實現。-Sensorless control of a 3 phase BLDC (Brushless DC) motor using a trapezoidal commutation scheme with BEMF (Back-EMF) measurement obtained via a simple resistor divider. Closed
frediv
- EDA分频器代码vhdl例程，可用，方便理解-EDA divider vhdl code routines that can be used to facilitate the understanding of
fenpin2500
- 用VHDL写的分频器,分频大小为2500分频-Written with VHDL divider, size frequency frequency 2500
VerilogSourceCode
- 乘法器、除法器、多路选择器、编码器、BCD码转换、加法器、减法器、状态机、四位比较器、数码管、串口、跑马灯、电子钟-Multiplier, divider, multiplexer, encoder, BCD code converter, adder, subtractor, state machines, four more players, digital control, serial port, marquees, electronic clock
secondclock
- 本设计是基于altera公司的ep2s750FPGA芯片的秒表计数器，其中包含六进制计数器和十进制计数器和万分频器等模块。-This design is based on the company s ep2s750FPGA altera stopwatch counter chip, which contains six binary counter and decimal counter and 10,000 divider modules.
ddz
- 斗地主实用的算分器，不用纸了，有兴趣的可以-Landlords practical calculation divider, not paper, and are interested can try
UART
- VHDL语言写的串口发送、接收程序，根据晶振和相应的波特率修改分频器就可以实现！-Written in VHDL serial send, receive, process, according to crystal and the corresponding baud rate divider changes can be achieved!
program
- 此程序1000倍的数字分频器，进行数字分频-This program digital divider, the digital divide
FPGA-DEVIDER
- 基于FPGA的小数分频器的实现 频率合成技术是现代通讯系统的重要组成部分,他将一个高稳定和高准确度的基准频率,经过四则运算,产生同样稳定度和基准度的频率。-FPGA-based implementation of the fractional divider frequency synthesis technology is an important component of modern communications systems, he has a high stability and
NCDividerAndItsApplicationVHDLSourceeCode
- 用VHDL编写的数控分频器及其仿真结果图片。该程序能实现PWM波形输出以及产生正负脉冲宽度可调的方波输出。-Prepared by the NC VHDL Simulation results divider and pictures. The program can achieve positive and negative PWM waveform output and pulse width adjustable square wave output.
chufaqi
- 四位除法器：使用vhd实现四位的有符号除法器-Four division: Use vhd signed to achieve four of the divider