搜索资源列表
8253TIMER
- 8253定时器实现分频，1秒定时子程序调用-8253 timer, divider, one second timer subroutine call
fenpin
- fpga的分频器，占空比为50 ，输出方波，同步脉冲-fpga divider, 50 duty cycle, the output square wave, the sync pulse
fenpin
- 这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写-This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog
stm8_gpio
- 原创-STM8程序解拆二：GPIO 上电系统内部高速时钟默认为2MHz， 可选择不同的时钟分频值,观察LED亮灯速度-Original-STM8 program split two solutions: GPIO Power System Internal high clock defaults to 2MHz, Choose a different clock divider value, observe the LED lighting speed
wang
- vhdl语言的四位二进制除法器，带有详细的流程图及计算原理-vhdl language of four binary divider, with a detailed flow chart and calculation principles
FPGA_Divider
- 本源码是用verilog语言编写的FPGA的除法器和74LS138及D触发器模块。-The source code is written in verilog FPGA divider and 74LS138 and D flip-flop modules.
devider
- 分频器 可以实现1：3 1：1 的分频器 源代码-Divider can achieve 1:3 1:1 divider
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
div_clk17
- 手写时中分频，17分频，用状态机写成，之欧诺个两个过程语句简单明了易懂-Handwritten carve frequency divider 17, the state machine languages, the two processes Uno a statement, jianji8e clear and understandable
div_serial.v02
- Module and test bench for Serial Divider
chufaqi
- 用vhdl编写的N位除法器，适合初学者学习和编程- written in VHDL a N divider, suitable for beginners to learn and program
tongxinzongheshiyan
- 微波实验设计，设计波导滤波器和波导等功率分配器-Microwave experimental design, waveguide filter design and waveguide power divider etc.
clkNdiv
- 很经典的时钟分频代码，直接拿来可以使用 使用VHDL语言编写！-Very classic clock divider code can be directly used to use using VHDL language!
division
- 分频器,偶数分频 奇数分频 小数分频 不同方法实现不同种类分频 -Divider, even odd frequency divider fractional different ways to achieve different types of crossover
div
- 除法器设计，基于FPGA，实现除法运算，在实物上测试通过-Divider design, based on FPGA, to achieve the division on the physical test
xunfachufaqi
- 从原理到实现的循环除法器的Verilog代码-Circular divider from the principle to the implementation of the Verilog code
fdiv
- 数字分频器，可以按照自己的要求通过给定时钟产生任意占空比和频率的时钟。-Digital divider, according to their own requirements generated by any given clock duty cycle and frequency of the clock.
Divider
- xilinx 除法ip核调用 含测试程序 vhdl语言-xilinx ip nuclear division calls including test procedures vhdl language
fenping_VHDL
- 这是一个任意分频器 稍微改动里面的数据 就可以进行分频（VHDL编写）-This is a slightly altered any data inside divider can be divided by (VHDL written)
chufa
- 开放式实验，CPU实验除法器，一个简单的除法器-Open experiment, CPU test divider, a simple divider