搜索资源列表
Example23
- 设计一款多功能数字秒表的VHDL小程序，产生100Hz时钟的分频计数器-Design a multi-function digital stopwatch VHDL applet, generate 100Hz clock divider counter
Example22
- 设计了一款基于多功能数字时钟的小程序，产生1Hz时钟的分频计数器并正常运行-Based on a small program designed multifunction digital clock divider to generate 1Hz clock counter and running
shu-kong-fen-pin-qi
- 数控分频器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-NC divider source code and detailed documentation WORD, maxplus software running, pin has been configured, the chip is EP1K30TC144-3
Example5
- 一款基于FPGA的数控分频器的小程序，定义时钟信号，输入控制的数据，分频输出，波形观测输出。-An FPGA-based applet NC divider, the definition of the clock signal, the input control data, frequency output, the output waveform observation.
001
- 分频器的四连体数码管显示源代码以及对其分析-The four-piece divider digital display source code and its analysis
1X4_power_splitter2
- 此程序模拟了17X11的正方形光子晶体点阵作为能量偏分器的动态过程。-This program simulates a 17X11 square photonic crystal lattice energy as a partial divider dynamic process.
Alfc
- fdiv1.v 为异步加载分频电路设计源程序 fdiv1_sti.v 为仿真测试测试程序。 总的能实现电路设计EDA异步加载分频电路的设计并实现仿真。-fdiv1.v asynchronous load divider circuit design source fdiv1_sti.v for the simulation test program.
Clockdivider
- VHDL CODE FOR CLOCK DIVIDER
The-choice-of-precision-resistance
- 硬件设计中，电阻分压、同相放大、反相放大经常会遇到精密电阻选择问题，本程序按E-96标准给的精密电阻系列，输入对应参数，自动给出最佳的精密电阻组合。-Hardware design, the resistor divider, noninverting, inverting amplifier precision resistor selection often encounter problems, the E-96 standard procedure according to the pr
Wnd2
- 固定分割窗口的分隔线，C++精选学习源码，很好的参考资料。-Fixed split window divider, C++ source selection study, a good reference.
divider3
- 一个3分频器。可进一步改装成实际需要的分频器使用-a divider. Can be further converted into actual use of the Frequency Divider
divp5
- fpga上实现的最小是0.5分频的任意分频器-FPGA to achieve the minimum 0.5 hours are arbitrary frequency divider
10-sequence-detector
- 本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率-The system uses a 48MHz clock experimental box as the input clock, to get the counter frequency divider and serial sequence frequency detector
pdiv
- 数控分频器的功能是，当在输入端给定不同的输入数据时，对于输入的时钟信号有不同的分频比。-The function of this divider is when different input data is available at the input,there is different divider ratio for clk.
clock_speed
- fpga分频器设计。将高频时钟信号任意分频-fpga crossover design. The high frequency clock signal any divider
binarydivider
- matlab编写的二进制除法器，能够实现64位除法运算-matlab write binary divider, the division can achieve 64
SDivider16bit_V120
- 循环型除法器Verilog代码，带有8位小数，可使除法器固定长度，缩减时钟开销-Streamlined divider Verilog code, with eight decimal places, make fixed-length divider, reducing the overhead clock
CLOCK
- 数字钟——分频器，将开发板上的20MHZ的输入CLK转换成时分秒进位需要要到的1HZclk-Digital clock- divider, input CLK 20MHZ development board will be converted into minutes and seconds rounding need to go to the 1HZclk
Daliklis
- Calculation of resistive divider with displaying results to black DOS screen
div
- vhdl除法器 vhdl除法器 vhdl除法器 -divider vhdl vhdl vhdl divider divider divider vhdl vhdl vhdl divider divider