搜索资源列表
mvebu-corediv-clock
- Core Divider Clock bindings for Marvell MVEBU SoCs.
FPGA_CLK
- FPGA时钟分频的源代码，已经测试通过！-FPGA clock divider source code, has been tested!
clock18div
- Clock Divider, divfactor of 18
at91_matrix
- Slow Clock Divider Mask.
lab4
- s the design and simulation of a simple traffic light controller: The controller consists of a clock divider block, two sequential circuits: a timing counter and a signal generator (state generator), and a decoder. The counter is used to define a
freq_div
- //奇数倍分频器基于verilog HDL.-(ODD number)Freq Divider based on Verilog HDL.
cvmx-helper-jtag
- Clock divider for QLM JTAG operations. eclk is divided.
CLK_div
- 用verilog写的分频器，包括16分频，8分频，4分频，2分频等，代码简单，效率高，个人感觉很实用且对初学者很有帮助-Written in verilog divider, including 16 points frequency, frequency eight points, 4 points frequency, frequency division 2, etc., the code is simple, high efficiency, personal feeling is ve
icst
- ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V). This frequency is pre-output divider.
pulseoximiter1
- 根据血液对光的吸收程度，通过感光器来收集数据，来测试心跳。 TSL235 感光器，放在手指下面，手指上面用光照，从而收集数据。需要配合配件TSL235 感光器，电路板，电阻。-You are going to interface a TSL235 to the FPGA. The TSL235 is a light-to-frequency converter whose output digital bitstream frequency is directly proportional
lab
- ADS tool used to design wilkinson power divider
berlin2-div
- Clock dividers in Berlin2 SoCs comprise a complex cell to input pll and divider. -Clock dividers in Berlin2 SoCs comprise a complex cell to input pll and divider.
rs780_dpm
- r600 engine clock entry enable post divider for Linux v2.13.6.
chapter9
- divider scl,d cfe lc,em l cme lrcm l ec lmrktn krnkelnl rlknecrlk clenrclke lkrclke lrenclek nkerncl lknrclke lkrencelrk lkcne ncrlekcnelk nlkercnlek-divider scl,d cfe lc,em l cme lrcm l ec lmrktn krnkelnl rlknecrlk clenrclke lkrclke lrenclek nker
frequency_divider
- Frequency Divider vhdl source code with test bench
divider
- Binding status: Unstable - ABI compatibility may be broken in the future.
global_reg
- TODO: TVC clock divider for Linux v2.13.6.
clk-corediv
- MVEBU Core divider clock.CORE_CLK_DIV_RATIO_MASK.
clk-frac
- The clock is an adjustable fractional divider with a busy bit to wait when the divider is adjusted.
4
- 数控分频器设计。包括偶数分频，和奇数分频。- NC divider design. It includes an even divide, and odd division.