搜索资源列表
cell_arch
- cell architecture for dual port ram
third
- codes for dual ported RAM
ug_ram_rom
- This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP c
Dual-port-RAM-data-acquisition
- 利用传统方法设计的高速数据采集系统由于集成度低、电路复杂，高速运行电路干扰大，电路可靠性低，难以满足高速数据采集工作的要求。应用FPGA可以把数据采集电路中的数据缓存、控制时序逻辑、地址译码、总线接口等电路全部集成进一片芯片中，高集成性增强了系统的稳定性，为高速数据采集提供了理想的解决方案。-Using traditional methods of high-speed data acquisition system design due to low integration, circuit
uart_ram
- 串口接收数据校样后存入双口ram,接收完整帧数据后，置中断，通知串口发送-After receiving proof serial data stored in dual port ram, receive a complete frame of data after the interrupt, serial port to send notifications
HPI-Communication-Design
- 介绍了TMS320VC5402的HPI主机接口原理,以一个简单的通信程序作为例子,详细说明通过HPI 口实现5402芯片内部的16 kB 双端口RAM与AT 89 C51单片机的通信过程. -Introduces the principle of TMS320VC5402 HPI host interface, a simple communication program as an example, a detailed descr iption of the chip to achieve
Example-b4-1
- 1.定制一个双端口RAM，DualPortRAM 2.在顶层工程中实例化这个RAM 3.实现这个工程，在Quartus II仿真器中做门级仿真 在ModelSim中对这个工程进行RTL级仿真-1. Customize a dual-port RAM, DualPortRAM 2. In the top-level project instantiate RAM 3. To achieve this project, do gate-level simulator in Qua
Dual_ram_verilog_CODE
- 写了FIFO中要用到的双口RAM的模块,FIFO中的RAM只用于读数据,输出数据,用写时针采集信号,读时针那一端不用读时针来采样.-Written to use the FIFO dual port RAM module, FIFO in the RAM is only used to read data, output data, the clock signal acquisition with write and read without reading that end of the h
IDT7026
- 双口RAM驱动程序及测试，具体设计时可参考，采用sem实现-Dual-port RAM and test driver
QuartusII_IP_Core
- 以设计双端口RAM为例说明QuartusII中利用免费IP核的设计的详细教程-To design dual-port RAM as an example of the use of a detailed tutorial QuartusII free IP core design
dual_port_ram
- True dual port ram VHDL implementation
Synchronous-FIFO
- FIFO是英文FIRST-IN-FIRST-OUT的缩写，是一种先进先出的数据缓存器，它与普通存储器的区别是没有外部读写地址线，这样使用起来非常方便，但是缺点是只能顺序读写数据，其数据地址由内部读写指针自动加1完成 FIFO的主要功能是基于对双口RAM的读写控制来完成的，根据双口RAM的数据存储状况产生空满信号。双口RAM指的就是能同时对RAM进行读写操作的RAM存储器 -FIFO is an abbreviation of the English FIRST-IN-FIRST-OUT,
dualporttst-1_1
- interfacing dual port ram in vhdl
Sunhaibo
- ＰＣＩ9054的读写，其中包括双口ＲＡＭ，以及寄存器的使用-PCI9054 read and write, which includes dual port RAM, as well as the use of registers
dual_ram
- 在ISE中测试双端口RAM的源码，结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
ram_2
- 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
fpga
- pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)