搜索资源列表
eth
- 用数字逻辑语言描述以太网，百兆以太网MAC和MII的verilog源码-With digital logic language to describe Ethernet
ethenete
- 基于verilog的三速以太网源程序，文件中包含源程序和测试程序。-tri_model ethernet source code based on vhdl languange, include source code and testbench in the file.
Chapter10-Sample
- 此代码是用Verilog实现的以太网接口-This code is an Ethernet interface implemented using Verilog
FPGADM9000AVerilog
- FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
FPGADM9000AVerilog
- FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
CycloneIII_ethernet
- CycloneIII + receive/transmit ethernet packets. Verilog
verilog_mac
- 该文档详细描述了以太网mac层的功能与实现，里面包括了verilog程序-The document describes in detail and implementation of Ethernet MAC layer functions, which includes the Verilog program
PHY_MDIO
- 光纤模块实现点对点通信，千兆网传输，基于FPGA，采用Verilog语言进行编程，实现千兆网模块的高速传输-Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module
K7_1M
- 用Verilog语言实现的以太网驱程，可最多实现8个以太网，外加PHY后，可实现ping操作-Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping
verilog-ethernet-master
- sivasankar is a good boy,,, njknsdjnjkgnjskn sjnkdnsgkjndjks jdskgnskdndgksj ksnklgnkl
ethmac10g_latest.tar
- ethmac10g_latest是用verilog编写的10gbps的以太网mac，对工程开发非常有用！-ethmac10g_latest is written in verilog 10gbps Ethernet mac, very useful for the development of the project!
ethmac10g_latest.tar
- 10G高速以太网mac VERILOG源码 可仿真可实现-10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation
eth
- 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
xge_mac_latest.tar
- 用Verilog编写的以太网控制器，可以使用，里面是全部verilog源码-Ethernet controller based on Verilog, can be used directly, all verilog files
ethernet_test
- 以太网FPGA通信,verilog代码，实现双向通信-Ethernet FPGA communication
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
UDP
- 利用verilog语言写的基于千兆网卡的UDP协议驱动-Use verilog language written based Gigabit Ethernet UDP protocol driver
14_ethernet_test
- 这是利用FPGA实现对以太网传输的控制。FPGA为Spartan 6 LX16，以太网芯片为RTL8211。千兆传输速率。语言为Verilog，但没找到这一选项，故选择了最接近的VHDL-This is achieved using the FPGA Ethernet transmission control. FPGA for the Spartan 6 LX16, Ethernet chip RTL8211. Gigabit transmission rate.
ETH_GEN_CHK
- Ethernet packet generator and check (verilog),for Ethernet design purpose!
kcu105_sgmii_over_lvds
- sgmii use verilog coding,and can work 1000M ethernet