搜索资源列表
16550
- UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。
Fifoed_avalon_uart_9.3
- Altera真正可用的带FIFO的UART组建。-Altera FIFO UART
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
FIFO_altera.v
- FIFO for Altera Cyclone II or Cyclone III on memory blocks. Length of FIFO can be changed.
aes3_rev1.0
- AES3在altera FPGA上开发的参考案例-AES3 Reference Design v1.0 The AES3/EBU reference design provides both a transmitter and a receiver. The receiver extracts the data and the clock an incoming AES3/EBU stream and stores the parallel audio data and
fifoed_avalon_uart
- 带fifo缓存的uart模块，适用与altera QSYS建构-uart module with fifo buffer for altera QSYS Construction
src
- ad9628配置，给出了spi配置接口的时序描述。设计中需要例化altera的fifo。(ad9628 configure with spi configuration timing,and there is a QuartusII fifo in the design.)