搜索资源列表
LAB31
- EDA基础_综合实验篇__实验三十一 FIR数字滤波器设计-The basis of comprehensive experimental articles EDA __ _ experimental FIR digital filter design 31
Filter
- FIR滤波器~在ISE下运行成功~格形滤波器-FIR
IIR_filter_design
- IIR滤波器的vhdl语言设计的简单滤波器-vhdl for iir filter
3x3_Median_test
- this is 3x3 median filter for test.-this is 3x3 median filter for test.
fir
- 是一个fir滤波器 其中使用了MAC单元去实现累加和乘法运算。-A fir filter which uses the MAC unit to achieve accumulation and multiplication.
eda
- 利用vhdl设计fir滤波器，有完整程序， 包含加法器，乘法器。-Design using vhdl fir filter, a complete program, including adders, multipliers.
MATLAB
- 基于 MATLAB 的语音信号分析与处理的课程设计.录制一段自己的语音信号，并对录制的信号进行采样；画出采样后语音信号的时域波形和频谱图；给定滤波器的性能指标，采用窗函数法或双线性变换设计滤波器，并画出滤波器的频率响应；然后用自己设计的滤波器对采集的语音信号进行滤波，画出滤波后信号的时域波形和频谱，并对滤波前后的信号进行对比，分析信号的变化；回放语音信号-MATLAB-based voice signal analysis and processing of the curriculum. Re
CIC
- 五阶CIC滤波器，用于降低数据传输速率。数字下变频技术不仅是软件无线电核心技术之一，还是中频数字化接收系统重要组成部分。数字下变频技术中广泛用到级联积分梳状滤波器（CIC滤波器）-CIC filter
LPfilter
- 16阶低通滤波器的VHDL实现，通过编译仿真，FPGA测试正确。-16-order low-pass filter VHDL implementation compile simulation, FPGA test correct.
FIR-filter-using-fpga-design
- 基于FPGA的高阶FIR滤波器设计4有matlab设计步骤 4.3更详细 第六章量化系数实例-FIR using FPGA ，QuartusII software
filter1
- 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hop
firfilter
- this is a coding file for FIR filter.
FIR
- 实现FIR滤波，利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out
mid_filter
- 中值滤波的实现，用于图像的预处理。取出图像噪声-Implementation of median filter for image preprocessing. Remove image noise
FIR_128
- FIR 128阶低通滤波器，由matlab仿真并在quartusII中实现-FIR 128 order low-pass filter
21840263filter-vhdl-code
- 这是我看到的一个关于FIR滤波器的资料，和大家分享。-This is what I see about FIR filter information to share with you.
LIP6301CORE_tv_filter
- TV Filter VHDL Souece code
FPGAdesignandFIRimplementation
- 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
fir
- 真正意思上的fir滤波器课程设计，基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases
20FIRfilterwithCSD
- 20阶FIR滤波器，用CSD编码对参数进行了设计-20-order FIR filter with CSD coding of the design parameters