搜索资源列表
jkcfq
- JK触发器，适合初学者用，上实验课使用杠杠的-JK flip-flop, suitable for beginners, using a lever on the experimental class! ! !
counter
- 用4个T触发器组成16位的计数器，FPGA实验ALTER DE2开发板自带光盘的案例程序解析-Four T flip-flop 16 of the counter, the case of FPGA experiment ALTER DE2 development board comes with CD-ROM program parse
Desktop
- 包括3:8译码器，D触发器组成的8位寄存器，8位乘法器，41多路选择器。-Including 3:8 decoder, the D flip-flop composed of 8-bit registers, the 8-bit multiplier, 41 multiplexer selector.
Basic-sequential-logic
- 用Verilog语言实现D触发器、累加器的功能-D flip-flop, the function of the accumulator using Verilog language
usb-modeswitch-1.1.5
- USB_ModeSwitch is (surprise!) a mode switching tool for controlling "flip flop" (multiple device) USB gear. Several new USB devices (especially high-speed wireless WAN stuff, there seems to be a chipset from Qualcomm offering that feature) have
VHDL-simple-examples
- 上传的几个VHDL程序：分别是各种功能计数器；使用列举类型的状态机，四D触发器，通用寄存器，伪随机比特发生器，简单的状态机。-Upload several VHDL program: are the various functions of the counter using the enumerated type state machine, four D flip-flop, the general-purpose registers, pseudo-random bit generato
SHIFT8
- 8位移位寄存器，利用元件例化，调用D触发器。-8-bit shift register using component instantiation, calling the D flip-flop.
cpld_kit_test
- VHDL code to implement basic gates and counter,Flip=Flop,Registers using Xilinx Platform.
the_design_basedonfpga
- 1. clkdiv 介绍时钟分频器的建模 2. counter 介绍计数的建模 3. dtrig 介绍D触发器的建模 4. jktrig 介绍JK触发器的建模 5. shiftreg 介绍移位寄存器的建模 6. ttrig 介绍T触发器的建模-The 1. Clkdiv modeling clock divider 2. Counter introduced count modeling the The 3. Dtrig 4. Jktrig introduce the mod
Dff
- D 触发器，数字电路中最基本的逻辑单元之一。很实用的程序例子-D flip-flop, one of the basic logics in the digital design, an instance of a Sequential VHDL codes
flipflop
- flip flop unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
D
- FPGA VERILOG实现 D触发器 -FPGA VERILOG D flip-flop
JK
- 带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器-With reset terminal, set end delay the 15ns CP' s response to the falling edge of the JK flip-flop
Trigger
- 理解触发器的概念及其触发机制。 2.掌握触发器的编写。-Understand the concept of the trigger and the trigger mechanism. Master the preparation of the flip-flop.
vhdlcode
- Vhdl code for d flip flop
pedometer
- 本文设计了基于加速度传感器的计步器，并通过仿真以及实际调试得到了相应的结果的记录。本实验首先通过加速度传感器检测目标物体的运动，产生脉冲，将脉冲放大后经过施密特触发器整型为方波，并给出了方波的调试电路图。然后编写程序，利用D触发器检测方波的上升沿，当上升沿到来时，计数，并对十位、个位分别编码，然后由使能信号交替控制数码管输出结果。本文给出了仿真以及调试的程序、结果。-This article is designed pedometer-based acceleration sensor and
VHDL
- 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器：用CASE语句 全加器： 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and comp
jk
- jk触发器，根据输入的信号J和K的不同，产生相应的输出-jk flip-flop, depending on the input signals J and K, and produces a corresponding output
cd4013
- CD4013是双D触发器，分别接成一个单稳态电路和一个双稳态电路。单稳态电路的作用是对触摸信号进行脉冲展宽整形，保证每次触摸动作都可-CD4013 dual D flip-flop, respectively connected as a monostable and a bistable circuit. Monostable circuit touch signal pulse broadening shaping, to ensure each touch action can
ffjk
- its a flip flop jk based in quartus II altera