搜索资源列表
jk
- jk触发器在rs触发器的基础上进行改进，可以将jk=1的输入状态定义为合法状态。-jk flip-flop in the rs flip-flop based on the improvement can be jk = 1 of the input state is defined as the legal state.
trigger
- D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
jitter_eliminate
- verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted
Flipflop
- flip flop project and explanation
NewFolder2
- Verilog and VHDL programs for sipo buffer,d flip flop etc
pisca
- machine with 16 possible states flip flop desmultiplexor language VHDL with fpga cyclone 3
bch
- Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
jicunqi
- 寄存器的VHDL实现，寄存一组二值代码，对寄存器的触发器只要求它们具有置1、置0的功能，在CP正跳沿前接受输入信号，正跳沿时触发翻转，正跳沿后输入即被封锁。-Register VHDL implementation, hosting a group of binary code, on the flip-flop registers only requires that they have set one, set 0 functions in CP are dancing along the
Rising
- example Rising Edge flip flop
latchesandflipflops
- Vhdl国外大学讲义，英文版，锁存器，触发器编写-Vhdl foreign university lectures, in English, latches, flip-flop to prepare
abc
- 本软件设计D触发器的目的和任务：1.使学生全面了解如何应用该硬件描述语言进行高速集成电路设计；2.通过软件使用、设计与仿真环节使学生熟悉EDA-VHDL开发环境；3. 通过对基本题、综合题的设计实践，使学生掌握硬件系统设计方法（自底向上或自顶向下），熟悉VHDL语言三种设计风格，并且培养学生应用VHDL语言解决实际问题的能力。 -The software design of D flip-flop of the purpose and tasks: 1. To enable students t
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
my_reg
- D触发器，Verilog实现，配有实验说明文档。-D flip-flop, Verilog implementation, with experimental documentation.
d_flipflop
- this is a general d-flip flop design in vhdl.
jiaozhibianmaqi
- 基于单片机的交织编码器，采用汇编语言编写，用D触发器产生m序列。-Encoder based on single chip interleaving, using assembly language, using D flip-flop produces m sequence.
Jkflipflop
- it s a vhdl code for jk flip flop in vhdl
Srflipflop
- it s a vhdl code for sr flip flop
7segmentos
- flip flop d laboratorio reporte
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
LabVIEW
- 四选一数据选择器.vi 3-8译码器.vi 全减器.vi 时钟.vi RS触发器.vi-4 Select a data selector. Vi 3-8 decoder. Vi Full reduction device. Vi Clock. Vi RS flip-flop. Vi