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shuzi
- 设计一个采用数字电路实现,对时,分,秒.数字显示的计时装置,周期为24小时，显示满刻度为23时59分59秒，并具有校时功能和报时功能的数字电子钟。电路主要采用中规模集成电路.本系统的设计电路由脉冲逻辑电路模块、时钟脉冲模块、时钟译码显示电路模块、整电报时模块、校时模块等部分组成。采用电池作电源，采用低功耗的芯片及液晶显示器，发生器使用石英晶振、计数振荡器CD4060及双D触发器74LS74，计数器采用同步双十进制计数器74LS160，锁存译码器是74LS248，整电报时电路用74LS74，74L
VHDLstudy
- 近期学习程序小结，对初学者比较有帮助，包括：四D触发器：74175 用状态机实现的计数器 简单的12位寄存器 通用寄存器 移位寄存器：74164 带load、clr等功能的寄存器 带三态输出的8位D寄存器：74374等 -Summary of recent learning process, more helpful for beginners, including: four D flip-flop: 74 175 with a simple state machine im
vb6.0andsqlserver2005
- 医药的进货、销售和库存管理包含一个触发器。文件里包含实验报告、实验代码、odbc源的配置-Medicine purchases, sales and inventory management includes a flip-flop. File contains the lab reports, test code, odbc source configuration
jishuji
- 将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成一个FPGA芯片中模拟其功能，并研究其相互转化的方法。-The basic RS flip-flop, synchronous RS flip-flop, integrated JK flip-flop, D flip-flop while a FPGA chip analog integrated function, and to study their mutual transformation method.
zonggongcheng
- 三个结合起来的D触发器的vhdl，分别是电平触发，上升沿出发和下降沿出发。-Combining the three D flip-flop vhdl, respectively, trigger level, rising and falling edge start start.
cdma
- vhdl code for flip-flop,lfsr
Classic_flip_flop_logic_function_conversion_electr
- 触发器逻辑功能的转换经典电子资料Classic flip-flop logic function of the conversion of electronic data-Classic flip-flop logic function of the conversion of electronic data
40XX
- CD40XX系列芯片PDF资料汇总，含单片机嵌入式卡发常用译码、驱动、锁存、寄存器、触发器-CD40XX chips PDF fact sheets, including single chip embedded cards issued common decoding, driving, latches, registers, flip-flop
CODE3
- FLIP FLOP VERILOG PROGRAM
jk
- 触发器设计范例，JK触发器的VHDL实现-Trigger for example, JK flip-flop of VHDL implementation
DFFquartus
- D触发器 quartus实现 有RTL图-D flip-flop to achieve a RTL Figure quartus
DFFornet
- D触发器 功能 有可能很简单，没有什么其他复杂的结合，仅供参考，多多指教-D flip-flop simple adafdafdasfdafd
muhammadali_357
- T-flip flop lab done in our campus
D
- 利用时钟信号实现同步D触发器的功能的vhdl代码-Using D flip-flop clock signal to synchronize the function of vhdl code
8_dv
- 一个简单的触发器实现，调用的是IP核，比较简单，适合初学-A simple flip-flop implementation, called the IP core, relatively simple, suitable for beginners
01chufaqi
- 带同步清0、同步置1 的D 触发器 verilog语言描述的-0 with synchronous clear, synchronous set 1 D flip-flop verilog language descr iption
veriloghdllicheng135li
- Verilog的应用例程，包含了基本的硬件编程，加法器，触发器-Application of Verilog routines, including the basic hardware programming, adders, flip-flop
shiziluoji
- 三位二进制加1与加2计数器 ：三位二进制模5计数器。当外部输入X = 1时，计数器加2计数；外部输入X = 0时，计数器加1计数。“模5”为逢“5”进1计数。 原始条件：使用D触发器( 74 LS 74 )、“与”门 ( 74 LS 08 )、“或”门( 74 LS 32 )、非门 ( 74 LS 04 )，设计三位二进制模5计数器。 -The three binary counter plus 1 and plus 2 : three binary mod 5 counter. X =
BCD_COUNTER
- Binary Counting A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For eac
FIFO
- 这是用VHDL设计的一个8*9阵列的D触发器组成FIFO（first in first out）-This is a VHDL design using an 8* 9 array of D flip-flop composed of FIFO (first in first out)