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verilog
- Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
synchronization-clock-generation
- 引入了D 触发器的长帧同步时钟的产生,其是一个时钟分频的例子，特别提醒了如何在程序中引入触发器，适合初学者引用。-The introduction of the D flip-flop of long frame synchronization clock generation, it is an example of a clock divider, remind how the introduction of the program Trigger reference for begin
D
- 此程序为以D触发器为基础的电路连接图，用于证明与学习阻塞赋值与非阻塞赋值的区别，已仿真成功。-This procedure is based on the D flip-flop circuit connection diagram for the proof and the blocking assignments and nonblocking assignments to learn the difference between the simulation has been succes
Ppt0000000
- This presentation file describes about the sequential circuits and compares withe flip flop and shows how the sequential circuits works with flip flop.
78
- 几种触发器的verilog语言程序设立，初学者适用-Several of the flip-flop verilog language program set up, for beginners
System_Demons
- 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实
Trigger
- 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
asynchronous-sequential-circuits
- 利用基本RS触发器设计电平异步时序电路的方法 此文档帮助读者设计数字逻辑电路，并非VHDL语言实现-The use of the basic RS flip-flop design level asynchronous sequential circuits This document is to help readers design digital logic circuits, not the VHDL language
vhdl_codes
- D-flip flop vhdl implement code
Desktop
- 四D触发器，最优先级编码器和加法器描述的VHDl文件-Four D flip-flop, the priority encoder and adder descr iption of the VHDl files
async_reset_dff
- 异步复位的D触发器 vhdl fpga xilinx spartan-3e-D flip flop async-reset vhdl fpga xilinx spartan-3e
JK_flip_flop
- verilog编程的JK触发器，可以用modelsim进行仿真，附有测试程序-JK flip-flop
flip_flop
- 使用verilog语言，在FPGA开发工具ISE上实现触发器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the flip-flop function.
fli
- --- vhdl code of d flip flop ---- vhdl code of d flip flop ---
DflipflopSource
- Verilog实现的D触发器及其测试，同步异步的代码都具有，而且还拥有测试代码-Verilog implementation of the D flip-flop and test, synchronous asynchronous code, but also have the test code
dff1
- 本程序使用vhdl语言编写，能够使用ALTERA CPLD-EPM3128A 模拟出一个D触发器。-This program written in vhdl language, be able to use of ALTERA the CPLD analog-EPM3128A, a D flip-flop.
div16_dff
- 该项目用D触发器设计了一个基于VHDL的16分频的分频器，其中包括仿真时序图。-Of the project design with D flip-flop frequency divider 16 points based on VHDL, including simulation timing diagram.
frediv3
- 该工程设计了一个3分频器。电路结构由D触发器和与非门组成，包括工程完整，时序仿真图。-The project has designed a 3-divider. The circuit structure consists of a D flip-flop and NAND gate, including complete engineering simulation, timing diagram.
div16_tff
- 该工程设计了一个16分频的分频器，电路采用T触发器，已通过仿真。-The engineering design of a 16 frequency divider circuit using T flip-flop, through simulation.
dcfq
- D触发器，适合初学者，上实验课的时候用杠杠的-D flip-flop, suitable for beginners, on the experimental course of a lever! ! !