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介绍关于FPGA的浮点加法器运算单元设计-Information on floating-point FPGA-adder cell design computing
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浮点数高精度加法计算，最高可以算105位大家请放心使用-Calculation of high-precision floating-point adder, the maximum you can count 105 Please be assured that the use of
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it is verilog code for floating point adder
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Floating point adder
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the code describle a floating point adder with verilog
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浮点加法器论文
a paper of floating point adder-a paper of floating point adder
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floating point adder
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浮点加法器的用Verilog实现，32位的浮点加法器-Floating point adder Verilog
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floating point adder
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this a code for implimenting floating point adder on FPGA -this is a code for implimenting floating point adder on FPGA
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基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
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32位浮点加法器
verilog语言编写-32-bit floating-point adder verilog language
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这个fpadd程序应用verilog语言，实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look.
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VERILOG CODE FOR FLOating point adder
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一个简单的加法计算器，可以实现浮点数的加法，适合java入门学员-A simple addition calculator, can implement floating-point addition, suitable for Java introduction to students
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该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
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32bit浮点数加法。只实现了两个正数的相加，通过modelsim仿真。开发环境为 Xilinx ISE。-32bit floating point adder. Only realized the sum of two positive numbers through modelsim simulation. Development environment for Xilinx ISE.
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一个简单的加法器的MFC应用程序，同时可以实现浮点数的操作。-A simple adder MFC application, also can realize the operation of floating point Numbers.
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能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
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32 bit floating point adder with testbench
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