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altfp_mult_DesignExample_ex
- 浮点数乘法 verilog语言编写 可直接调用-Floating-point multiplication verilog language
altfp_log
- 浮点数 log运算模块 verilog语言编写 可直接调用-Log floating point arithmetic module can directly call verilog language
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
altfp_matrix_mult
- 浮点数 矩阵乘法模块 verilog语言编写 可直接调用-Floating-point matrix multiplication module can directly call verilog language
FFT
- VERILOG CODE FOR FLOATING POINT 8 POINT FFT
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算,包括全部工程以及Verilog 源码,经验证,该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
Verilog_add_div_multi_exp
- 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
float_int
- 自己编写的,浮点数与整数之间的转换的Verilog HDL实现-Written by myself, it is converted into Verilog HDL integer floating point implementation
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
floatadd
- 32位浮点数加法,使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
Kalman Filter
- 实现单精度浮点的kalman滤波器的verilog方法(Verilog method for realizing single precision floating point Kalman filter)
fpmul
- Verilog语言编写的单精度浮点数乘法器(The Verilog language of single precision floating point multiplie)