搜索资源列表
Ram_FIFO
- 利用Basys2 FPGA 开发板实现FIFO_ram -Basys2 FPGA development board to achieve FIFO_ram
verilog-example
- 以前用XC3S400AN的fpga开发板做的实验，供新手参考-XC3S400AN fpga development board to do the experiment, for the novice reference
fPGA_LED
- FPGA开发板做的一个简单LED驱动，使用Verilog语言实现- This is an example of a simple 32 bit up-counter called simple_counter.v It has a single clock input and a 32-bit output port module simple_count(input clock , output end of module counter
bin2chuan
- 在FPGA开发板上座的输出波形的实验，输出波形通过示波器显示出来-// This is an example of a simple 32 bit up-counter called simple_counter.v // It has a single clock input and a 32-bit output port module simple_count(input clock , output reg [31:0] counter_out) always
sequence_detector
- 序列检测器的设计师用Verilog语言实现的，实现了状态之间的有效处理，在FPGA开发板上可运行-module xulie_check(clk,rst,x,y) output y input clk,rst,x reg y reg [2:0] state parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7 always@(posedge clk or negedge rst)
DEMO_V
- 黑金FPGA开发板的DEMO 程序，适合初学者入门级， quartus12.0下面编译通过-The black gold FPGA development board DEMO program
VHDL_LCDPUART_example10
- VHDL实现的串口通讯和1602液晶显示的实验程序，可以从PC发送数据到FPGA，并在LCD上显示，也可从FPGA开发板上键入数据，在LCD上显示，并通过串口发送到PC机上，适合初学者入门使用，-VHDL realization of the experimental program of serial communication and 1602 LCD, you can send the data from the PC to the FPGA, and displayed on the L
digitalclock_demo
- 该程序适用于xilinx公司的FPGA开发板，spartan3E系列250型号 通过verilog编程实现数字钟的功能，下板子验证可用！-This procedure applies to xilinx FPGA development board Series 250 Model spartan3E digital clock verilog programming under the board to verify available!
Columbia-University-on-VGA-video
- vga的现实原理与实际应用，基于DE2 FPGA开发板的应用，很透彻，很贴切，很有参考价值-vga reality principle and practical application, based on the application of the DE2 FPGA development board, very thorough, very appropriate, great reference value
xuliejianceqi
- 在FPGA开发板上用硬件描述语言实现一个状态序列检测器，比如边沿检测器等-FPGA verilog
jiaotongdeng
- 交通信号灯自动控制器,能下载到FPGA开发板，自动交通灯控制程序，由VHDL编写，环境为QUTUS2-Traffic signal controller, can be downloaded to the FPGA development board, automatic traffic light control procedures, written by VHDL environment QUTUS2
DE2-70
- DE2-70 FPGA开发板学习实例及代码，Verilog HDL-DE2-70 FPGA development board learning examples and code, Verilog HDL
tftlcd
- 正点原子tftlcd的fpga驱动（三个tft*.v)，还包括了大西瓜fpga开发板的数码管驱动和一个运行屏保的小功能，quartus6.0下开发。除了初始化代码，其他控制与主流tftlcd兼容。-verilog languge tftlcd driver
FA161-SCH
- 联华众科FPGA开发板FA161核心器件为 Altera Cyclone系列FPGA EP1C6，FA161板载有SDRAM，SRAM，FLASH方便制作各种应用，开发板所带资料中包括了上位机与开发板USB通信，上位机与开发板以太网通信，上位机与开发板串口通信例程。FA161板载有USB 1.1，USB 2.0(CY7C68013A)接口，以太网接口(RTL8019AS)。FA161上可以进行HDL程序开发，可以进行nios ii程序开发，可以结合MATLAB制作DSP Builder应用。FA
led_cycle
- 本程序实现了花样流水灯设计，并成功的在FPGA开发板上进行验证。-Figure running water light
sing
- 实现了蜂鸣器唱歌的功能，并在FPGA开发板上实现-Realized the function of buzzer singing and implementation on FPGA development board
two_color
- 实现了双色灯的点亮功能，并在FPGA开发板上实现-Has realized the double color lamp light up function, and implementation on FPGA development board
more_color
- 实现了多个灯的点亮功能，并在FPGA开发板上实现-Implements multiple lights light up function, and implementation on FPGA development board
pll_use
- 实现了用FPGA调用pll的功能，并在FPGA开发板上实现-Implemented with FPGA calls to the function of the PLL and implementation on FPGA development board
hvdl
- 实现60秒秒表功能，代码简单，可扩展，可操作，已在FPGA开发板上实现-Achieve 60 seconds stopwatch function, the code is simple, scalable, operable in FPGA development board to achieve