搜索资源列表
latches-
- 锁存器，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-Latch, FPGA experimental alter the DE2 development board comes with the CD case tutorial programming resolution
Finite-State-Machines
- 状态机，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-State machine FPGA experiments alter the DE2 development board comes with a CD case tutorial programming resolution
Digital-tube
- 数码管显示，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-Digital display, FPGA experimental alter the DE2 development board comes with a CD case tutorial programming resolution
lab8
- 有关fpga存储器的设计，开发板为DE2-70，内附word文档说明-Fpga memory designs, development boards for the DE2-70, containing a word document descr iptions
DigiClock_v1.0
- 多功能数字钟：包含默认模式、设置模式、闹钟模式和跑表模式。已在ISE10.1工具烧录成功，烧录开发板Xilinx Spartan 3 xc3s400 pq205 speed -4 开发板烧录成功-Multi-function digital clock: contains the default mode, setting mode, alarm mode and stopwatch mode. The source code has been successfully burned in IS
FPGAhandbook
- FPGA黑金开发板用户手册(包括引脚编码适用于Cyclone II）-The descr iption of FPGA handbook by HEIJIN
Virtex-5-
- 好用的Virtex-5 开发板与套件，基于fpga的嵌入式开发平台-Easy to use Virtex-5 development board with a package based on fpga' s embedded development platform
09_uart2
- PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示 -On the PC, open the serial port on a PC debugging assistant to send a character to the development board (in the middle connected by serial cable) FPGA received character back to the s
calculator
- 基于赛灵思的spartan-3e开发板的语音智能计算器的设计，开发语言verilog，开发软件ISE，可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解！-Development board based on Xilinx spartan-3e voice smart calculator design, development languages Verilog, developing software ISE, according to
ADDEE2_NETl
- Altera的DE2开发板上的DM9000A网络FPGA接口及及其驱动driver程序源码，还有 Demo程序源码 -Altera' s DE2 board DM9000A network FPGA interface and its driver driver program source code, as well as the Demo program source code
june2010_1
- 一种新型SOPC自动指纹识别系统设计，：本文设计了一种基于SOPC的新型结构的自动指纹识别系统。通过对指纹处理整体流程的选择和优化，把耗时较多的指纹预处理部分整体硬件化，耗时较少的匹配部分软件化，使得系统处理速度有了显著提高，1.5s内可以完成一幅指纹图像的预处理，3s内可以完成一幅指纹图像的比对。本设计使用Quartus II软件完成了系统模块设计及仿真，使用NiosⅡ IDE软件完成了软件代码的实现，并在以Altera 公司的Cyclone II FPGA芯片为核心的DE2开发板上实现了整个
mar2010
- 基于FPGA的单精度浮点数乘法器设计，本文设计了一个基于FPGA的单精度浮点数乘法器。乘法器为五级流水线结构。设计中采用了改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构，减少了部分积的数目，缩短了部分积累加的耗时；提出了对尾数定点乘法运算中Wallace树产生的2个伪和采用部分相加的处理方式，有效地提高了的运算速度；并且加入了对特殊值的处理模块，完善了乘法器的功能。单精度浮点数乘法器在Altera DE2开发板上进行了验证，其在Cyclone II EP2C35F672C6器
pingpangqiu
- 本文使用 FPGA 芯片来模拟实际的乒乓球游戏。本设计是基于 Altera 公司的 FPGA Cyclone II 芯片 EP2C5T144C8 的基础上实现，运用 Verilog HDL 语言编程，在 Quartus II 软件上进行编译、仿真，最终在开发板上成功实现下载和调试。 -This article uses the FPGA chip to simulate the actual game of table tennis. The design is based Altera
DSP2812SCH
- 这是前面几个FPGA例子的开发板原理图，是DSP&FPGA综合性开发板，供大家参考学习-This is the first few examples of FPGA development board schematics, a comprehensive DSP & FPGA development board, for your reference learning
DE2platform-introduction
- 基于FPGA的de2平台介绍，包括DE2开发板各部分的功能和简单应用。-Introduced, including the de2 platform based on FPGA the DE2 board functions and simple application.
uart2
- PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示-PC, open the serial debugging assistant to send a character to the development board (the middle through the serial line connected) FPGA received after the character, and posted back to t
8-SEG-LED-Board
- 基于FPGA的EPM 1270芯片开发板的8 SEG LED Board Verilog程序，已通过测试，能正常使用，引脚已配好。-Based the EPM 1270 chip FPGA development board 8 SEG LED Board Verilog program has been tested normal use, the pin with a good.
red-logic-Slave-FIFO_USB
- 红色飓风开发板程序 Slave FIFO_USB， cy68013加FPGA源码，完成USB通讯 -Red hurricane development board procedures the Slave FIFO_USB, cy68013 plus FPGA source code, complete USB communication
Function_clock_generate
- 基于FPGA实现的实时闹钟，在DE2—115开发板上通过验证，实现报时，定时，时间调整等功能-Based on verified DE2-115 development board FPGA to achieve real-time alarm, timekeeping, timing, time adjustment
lab1
- F:\FPGA\Spartan 3E开发板的实验例程-开发板实验例程-F: \ the FPGA \ Spartan 3E development board test routines- development board test routines