搜索资源列表
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
dds_new
- 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级-Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
AIC
- 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/
sin_sample_clock
- EP2C CYCONLY 系列的FPGA时钟测试程序，是由内部时钟分频后，点亮数码显示灯来证明的。绝对好用的程序。编写的执行效率很高-EP2C CYCONLY series FPGA clock test procedure is determined by the internal clock frequency, the lamp lit digital display to prove. Absolute-to-use program. The preparation of the imp
LVDS_DDR_List_FPGA2
- FPGA芯片与ADI公司的AD9779之间的通信，总共有四个通道，68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
TKC7524jiekoudianluchengxu
- 根据TLC7524输出控制时序，利用接口电路图，通过改变输出数据，设计一个正弦波发生器。TLC7524是8位的D/A转换器，转换周期为 ，所以锯齿波型数据有256个点构成，每个点的数据长度为8位。.FPGA的系统时钟为 ，通过对其进行5分频处理，得到频率为 的正弦波-TLC7524 output under the control of timing, the use of interface circuit, by changing the output data, the design o
clock
- 用FPGA制作的电子时钟，程序简洁，时钟走时精准，带整点报时功能-FPGA with the production of electronic clock, the procedure is simple and accurate travel time clock, time zone function of the whole point
clock
- FPGA实现电子时钟，可以设置为12小时制和24小时制！-FPGA electronic clock can be set to 12-hour system and 24-hour system!
AlteraCycloneIIFPGAStarterBoard
- Altera Cyclone II FPGA Starter Board原理图-Altera Cyclone II FPGA Starter Board Schematic
FPQ
- 基于FPGA的数控分频器，可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.
2
- FPGA设计中几个基本问题的分析及解决 多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the d
DP83640
- IEEE 1588 PTP 硬件支持功能的以太网收发器，时钟精确性能表现非凡无论选用何种微控制器、FPGA或ASIC，DP83640的加入都可确保系统设计的高度灵活性，并实现高达8ns的精确度-IEEE 1588 PTP hardware support Ethernet transceivers, clock accurate performance, whether extraordinary selection of the microcontroller, FPGA or ASIC, D
LEDVHDL
- 8.2 LED控制VHDL程序与仿真 本节分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序。 1. 例1：FPGA驱动LED静态显示 --文件名：decoder.vhd。 --功能：译码输出模块，LED为共阳接法。 --最后修改日期：2004.3.24。 -8.2 LED control and simulation of VHDL procedures introduced in this section of the LED using FPGA st
clock
- 含有电子钟，可以设定时间，调整时间，已经调试成功，用于fpga上-electic clock
clock
- 基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock
digitalwatch
- Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The e
FPGAclk
- fpga时钟，是入门的基础；希望对大家有帮助！-fpga clock, is the entry of the base want to help you!
clock
- 用VHDL写的带有小时，分钟，秒的电子钟，已在FPGA开发板上调试运行过，显示very well!-Written in VHDL, with the hours, minutes, seconds, the electronic clock has been running in the FPGA development board debugger before, show very well!
clock2Hz
- this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga.