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alarm_clock
- alarmclock fpga clock
clock
- 利用FPGA控制,数码管显示,实现数字钟的功能,经过试验论证,完全可用。-Using FPGA control, digital display, digital clock function, demonstration, tested and fully available.
vhdl
- 用vhdl语言实现的电子时钟加闹铃,程序结构紧凑,由于FPGA的时钟很快,所以时钟非常准确-Electronic clock and alarm, vhdl language program structure is compact, very quickly due to the FPGA clock, the clock is very accurate
clock-design-verilog-Fpga
- verilog设计的计时表,数字电路设计,FPGA-using verilog design watch, digital circuit design, FPGA
digital-clock
- VHDL语言的数字时钟的设计,用于FPGA的数字时钟的设计。-VHDL language digital clock design, FPGA for digital clock design
clock
- 用FPGA实现的电子钟代码,可实现年、月、日、时、分、秒计时及整点报时功能,可以手动设置时间-FPGA implementation of the electronic clock code, year, month, day, hours, minutes, seconds, chronograph, and the whole hour, you can manually set the time
zhong
- 基于FPGA的数字时钟,能校时、校分,整点报时。-fpga clock
clock
- 本设计主要研究基于FPGA的数字钟,要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能,可以对年、月、日、时、分及秒进行单独校对,使其校正到标准时间。-This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has
clock
- 采用FPGA实现数字钟功能,包括调时调分整点报时等功能。-FPGA Implementation of a digital clock function, including the tune when the tune points the whole point timekeeping functions.
xfest09_clocking_10_27
- XILINX公司FPGA时钟设计技巧,绝版好资料-XILINX FPGA clock design skills,Out of print good information
FPGA-digital-clock-design
- 这是基于FPGA的多功能数字时钟设计。是一篇论文,看看吧。-This is the design of FPGA-based multi-function digital clock. A paper, look at it.
Clock
- FPGA入门程序,简单的FPGA驱动数码管显示及计时器程序。-It s very simple,for rookies.
degital-clock
- 基于FPGA 编写的数字钟程序,分为 时计时器,分秒计时器,选择器和译码器 4个模块-degital clock
FPGA-based-multi-Divider
- 分频器是指使输出信号频率为输入信号频率1/N的电子电路,N是分频系数。在许多电子设备中如电子钟、频率合成器等,需要各种不同频率的信号协同工作,常用的方法是以稳定度高的晶体振荡器为主振源,通过变换得到所需要的各种频率成分,分频器是一种主要变换手段。 本文当中,在分析研究和总结了分频技术的发展趋势的基础上,以实用、可靠、经济等设计原则为目标,介绍了基于FPGA的多种分频器的设计思路和实现方法。本设计采用EDA技术,以硬件描述语言VHDL为系统逻辑描述手段设计文件,在QuartusⅡ工具软件环境下
clock
- 利用verilog语言在fpga上实现不同分频器的设计,适合初学者学习-Verilog language in different divider on the fpga design, suitable for beginners to learn
vhdl-clock-with-vga-output-for-Nexys-2
- Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl.
clock
- vhdl语言实现的时钟功能的quartus工程。在FPGA上运行可以得到时钟效果,并有调节功能。-vhdl language to achieve clock quartus project. Can get the clock running on the FPGA results, and regulatory function.
stepping-motor-and--Digital-clock
- 在FPGA上运行,控制步进电机和数字时钟的程序-Running on the FPGA to control the stepper motor and digital clock program
Clock-Management-Tips
- FPGA 多时钟设计中的时钟管理贴士 摩托罗拉半导体 Sylvain Haas 写的-Clock Management Tips on a Multi-Clock Design
clock
- 实现FPGA的数字钟的实现,具有小时、分、秒等功能-FPGA digital clock, with hour, minutes, seconds and other functions