搜索资源列表
fpga
- 多功能数字钟，具有年月日时分秒功能，同时能校时，1个八段数码管显示-Multifunctional digital clock with date, hour function, and can school, an eight digital tube display
FPGA-BASYS2
- 基于FPGA BASYS2开发板的数字钟，能够实现计时，时间校准，闹钟，整点报时等功能。-Development board based on FPGA BASYS2 digital clock, to achieve timing, time calibration, alarm, hourly chime functions.
clock
- 基于ＦＰＧＡ平台，通过数码管显示完成秒表的功能。通过按键，可实现从０到９９的正向计数或反向计数。-FPGA-based platform, through the digital display to complete the stopwatch function. Through the key, can be realized from 0 to 99 counts forward or reverse counting.
clock
- fpga数字钟程序vhdlyuyanxiede -fpga digital clock procedures
FPGA-verilog-digital-clock
- FPGAverilog数字时钟,基于quartal ii 下的数字时钟电路程序-FPGA verilog digital clock
electronic-clock
- 基于FPGA的电子时钟的七段数码管显示+按键控制verilog程序-FPGA-based electronic clock seven-segment LED display+ button control verilog program
digital-clock
- 基于FPGA的数字时钟设计，时钟可以按设定好的时间进行自动计时，FPGA板子上可以显示相应的时钟数字，是数字电路课程的一个课程设计，也是对于VHDL语言的一个熟悉过程.-FPGA-based digital clock design, the clock can be a good time to set automatic timing, FPGA board clock can display the corresponding figure is a digital circuit des
digital-clock
- fpga verilog 2位数码管显示仿真及说明-fpga verilog 2 digit LED display and descr iption of the simulation
led_new
- 时钟分频 FPGA 键盘实验操作程序 谢谢大家 我真的是来下载程序的 -clock FPGA clock div
digital-clock
- 基于qurtusII的用FPGA设计的可控数字闹钟-digital alarm clock
clock
- 基于FPGA的一个数字时钟的实现，还有硬件仿真，需要用quartusii_60_sp1_web_edition软件实现。-FPGA-based implementation of a digital clock, as well as hardware emulation, you need to use quartusii_60_sp1_web_edition software.
EDA-clock
- 基于FPGA的时钟设计,主要能实现计时和日历功能-The clock design based on FPGA, the main can realize clock and calendar function
cnt60
- 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.
clock-
- 这是一个小小的时钟程序，在vhdl的环江夏运用fpga语言来编写-This is a small clock procedures, in vhdl fpga ring jiangxia use language to write
digital-clock
- 用FPGA实现数字钟功能，用VHDL语言编写，含有课程设计报告-FPGA digital clock
clock
- fpga仿真，关于时钟，所有文件都在里面，可以直接用-fpga，simulate clock，all files in it
digital-clock
- FPGA写的多功能数字钟，非常适合初学FPGA的同学，作为参考吧。-FPGA write multifunction digital clock, FPGA is ideal for beginner students, as a reference to it.
FPGA_CLK
- FPGA时钟分频的源代码，已经测试通过！-FPGA clock divider source code, has been tested!
spi_slave
- SPI功能模型，可以用于SPI的仿真验证工作，对其进行测试-Now for the SPI slave in the FPGA. Since the SPI bus is typically much slower than the FPGA operating clock speed, we choose to over-sample the SPI bus using the FPGA clock. That makes the slave code slightly more compli
clkdiv
- 对于fpga的时钟分频，编程方法，简单易懂，赠给各位学习fpga的同志们-For fpga clock frequency division, programming method, and easy to understand, to your learning fpga comrades