搜索资源列表
SBQfpga
- 自制掌上示波器的制作中，FPGA部分的程序，包括FIFO，PLL的使用，以及FPGA软核的使用-Made in the production of handheld oscilloscopes, FPGA part of the program, including FIFO, PLL' s use, and the use of soft-core FPGA
FIFOyibusheji
- 讲述FPGA的异步FIFO设计，是学习型文档，个人认为很有意义-About FPGA s asynchronous FIFO design is a learning document, personally think that makes sense
uart_1203_4
- MUC+fpga 串口扩展，已调试通过，4路串口共用中断，收发fifo，波特率可调，其他的可以自己添加，网上类似资料极少，极具参考价值！只提供verilog源码！-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, o
asdhbja
- 异步FIFO源代码 vhdl基于FPGA的设计，绝对值得一下，非常不给力的20 个字-vhdl code of asynchronous FIFo
FIFOUART
- fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
NIOSII_TFT_COMS
- 带FIFO的ov7670 FPGA应用程序，经测试可用，望采纳。-With the FIFO the ov7670 FPGA applications used by the test, looking to adopt.
Core_fifo_w
- FPGA写FIFO操作,然后把FIFO里的数据送到编码器里编码成PAL格式，输出-write a picture to the fifo odd and evea ,then it can be used to encode into the PAL to display
fifo_232
- 基于fpga串口fifo设计，经本人测试，可用-Fpga serial fifo design after my test, available
eetop.cn_emif_brg
- fpga与DSP通过emif接口通信，fpga内部通过fifo进行数据缓存-fpga with the DSP through emif interface communication, fpga internal data cache by fifo
uartfifo
- FPGA采用FIFO实现UART，对于大量异步数据的采集传输很有帮助-A usart design of FPGA using fifo,it can be used in massed asychronous data collect.
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
cpld-usb
- usb-fpga通讯，从cpld到usb协议芯片slave fifo的通讯过程指导。-The usb-FPGA communication from the CPLD to usb protocol chip slave FIFO communication process guidance.
SDRAM_FPGA
- 这个是SDRAM的控制程序，包括包括UART和FIFO模块，适合FPGA开发人员看，也适合初学者学习。-This is the SDRAM control procedures, including including UART and FIFO module, suitable for FPGA developers look, but also suitable for beginners to learn.
rd_wr_fifo_tb
- 68013 slave fifo 读写测试程序 fpga开发-68013 slave fifo
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
3333333
- 基于vhdl语言的同步fifo的宏模块调用程序，可学习fpga的宏模块调用方法-Synchronous fifo vhdl language-based macro block the calling program, can learn fpga macro module calls methods
syn_fifo_use
- fpga 同步fifo调用 vhdl语言编写syn fifo use -synchronous fifo call fpga vhdl language syn fifo use
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
EZ_USB_LOOPBACK
- 本程序：EZ-USB在slave fifo模式下，利用FPGA控制EZ-USB的数据读写-This program: EZ-USB in slave fifo mode, use the EZ-USB FPGA control data read and write
SDRAM_Test5
- 基于EP1C12Q240C8的红色飓风二代FPGA开发板的SDRAM测试程序，含有写入和读出FIFO，串口UART,数据发生模块。-Based EP1C12Q240C8 a red hurricane II FPGA development board SDRAM test program, containing written and read FIFO, serial UART, data generation module.