搜索资源列表
fifo
- CAN总线，DSP+FPGA+SJA1000架构，FPGA负责逻辑设计,此文件内有FPGA负责dsp和sja1000通信-CAN bus, DSP+ FPGA+ SJA1000 architecture, FPGA logic is responsible for the design, FPGA is responsible in this document have dsp and sja1000 Communications
Altera-FIFO
- 介绍了Altera的FPGA的FIFO的功能与介绍-Introduction of Altera' s FPGA capabilities with the introduction of the FIFO
FPGA-Source-Code_VHDL
- cypress fx2lp slave fifo fpga控制端源码-source code of FX2LP_SLAVE_FIFO CONTROLLER S
FIFO
- 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
uart
- 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
uartverilog
- FPGA利用串口、FIFO实现串口收发数据(FPGA using serial port, FIFO serial transceiver data)
CCD_Array
- Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
parameter_uart_rx
- 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data wi
syn_dp_fifo.v
- 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
sp6ex19
- FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
SDRAM缓冲测试程序
- 对FPGA的SDRAM进行测试，主要是实现FIFO-SDRAM-FIFO的数据传输(Test the SDRAM of the FPGA)
20170808_fifo_xc5v_v1.5
- FPGA通过fifo进行数据的载入载出，实现数据的暂时存储和传递(FPGA through fifo data loading and unloading, to achieve temporary storage and delivery of data)
eetop.cn_FIFO_Buffer
- 异步FIFO的Verilog程序及其测试程序(FPGA/Verilog FIFO_ASYN)
fifo_FPGA
- 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)
tx_rx_fifo
- 通过串口将接收到的数据存入fifo,fifo存满后使能串口发送功能，将接收到的数据发送出去(Use fifo to realize the receive and send function of the uart. The function is no problem.)
13_usb_test
- READ 16BIT DATA FROM EP2 FIFO AND SEND TO EP6 FIFO
fifo_test
- fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
usb slave fifo 测试程序 cy7c68013
- usb slave fifo altera FPGA测试程序 cy7c68013方法的示例程序！可以参考！
tx_interface_project
- 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve