搜索资源列表
fulladd4
- 全加器代码和测试激励文件，优化的全加器，占用FPGA资源少-Full adder code and test incentives
pine_line_adder8
- 8 位全加器的设计，采用多pipeline设计方法-8 full adder multi-pipeline design
qjq
- 基于VHDL的全加器程序，用门电路实现两个二进数相加并求出和的组合线路，就是求二进制数矢量加法的。-Full adder VHDL-based program, with gates to achieve two binary numbers together and find a combination of lines and is seeking the binary vector addition.
adder6
- Full Adder 6 bit - Made out of 2 half adder and one adder
jiafaqi
- 一位全加器的VHDL程序，上学时实验用的，很简单的，初学者可以-A full adder VHDL program, school experiment, very simple, beginners can look
EDAlabor3
- 半加器到全加器，8421码到geleima转换。-Half adder to full adder, 8421 yards to geleima conversion.
full_adeeeder
- FPGA上的一个全加器实例程序，通过测试，可以直接运行在fpga开发板上。-A full adder example on FPGA program, through the test, can be run directly on the FPGA development board.
FASwitch
- Full Adder Design in Switch level Modelling using Verilog
quanjiaqi
- 此程序是用VHDL语言描写的全加器程序，从顶层开始设计的-This procedure is described using VHDL full adder program, designed to start from the top
VD1
- VHDL code of full adder
VHDL-8-wei-quan-jia-qi
- 原理图输入法实现8位全加器，内含vhd源码文件和一份word介绍文件，管脚配置已经完成，芯片为EPIK30TCI443-Schematic entry method 8-bit full adder, and a source code file containing the vhd file word descr iption, pin configuration has been completed, the chip is EPIK30TCI443
Example9
- 一个基于FPGA的四位全加器的小程序，输入两个二进制数并计算结果。-An FPGA-based four full adder applet, enter two binary numbers and calculations.
ex15
- 四位全加器的集成版图设计，基于tanner软件平台的layout设计，欢迎下载-The integration of four full adder layout, tanner software platform based on layout design, please download
carry_skip_adder_verilog
- 行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现-Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
full_adder
- full adder coding for multipliers
ADDER_8BIT_FOR_BCD
- 基于FPGA的由两个四位全加器合成的八位全加器 -Based on the synthesis of two four eight full adder full adder FPGA
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
full_adder
- design full adder by vhdl
05929500
- Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
VHDL
- vhdl adder full adder for basic tutorial