搜索资源列表
h_adder
- 基于两个半加器和一个异或门组成的全加器（资料中波形图为半加器的时序仿真图）-Based on two half-adder and an exclusive-or gate full adder (profile picture shows a half adder waveform timing simulation diagram)
full_adder
- a full adder verilog source created by two half adder
TEST1
- 在本实验中，用三个按键开关来表示 1 位全加器的三个输入（ Ai、 Bi、 Ci）； 用二个 LED 来表示 1 位全加器的二个输出（ Si， C）。通过输入不同的值来观察输 入的结果与 1 位全加器的真值表（表 1-1）是否一致。-In this experiment, three button switches to represent three input a full adder (Ai, Bi, Ci) two by two LED to indicate output a
wallacetree
- WALLACETREE USING FULL ADDER IN 45NM TECHNOLOGY
Multiplier
- 复用全加器来实现乘法器, 通过从右到左互为输入输出，实现低位计算。最左向高位输出。具体要求请参见附带的PDF。-Multiplexing a multiplier to achieve full adder, input and output by each other right to left, the least significant bits is calculated. Most left output to high. Specific requirements Refer to
2014011494
- FPGA嵌入式开发全加法器程序。二进制运算器及数码管扫描电路-FPGA embedded development full adder program. Binary calculator and digital tube scanning circuit
full_add4_ok_4quanjiaqi
- 本程序是用vhdl开发的实现全加器功能的程序。(This procedure is developed using VHDL to achieve full adder function of the program.)
hadder_1
- 用quartus9.0编写的一位全加器，自己设计，能有效运行出结果(Written in quartus9.0 with a full adder, their own design, can effectively run the results)
fadder_4
- 利用quartus9.0中元器件模块设计的四位全加器，能运行出结果(Quartus9.0 binary device using the design of four bit full adder, can run the results)
fadder_4v
- 利用quartus9.0中verilog语言实现的四位全加器，亲测有效(Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective)
lab1
- 用半加器搭建全加器 使用Verilog语言(Using a half adder to build a full adder, using the Verilog language)
ModelSim
- Implementing a full adder in ModelSim by using Verilog Language
add
- 一个用quartus原理图输入的全加器，(A full adder with quartus schematic input,)
full_adder
- 全加器，可以实现数据的加法运算，有来自低位的进位和向高位的进位。(Full adder, data can be added to the operation, there are low from the carry and to the high carry.)
EDAadd
- 全加器Full adder schematic waveform diagram(Full adder schematic waveform diagram)
add8
- 8*8位全加器的代码 verilog语言，包含测试文件(8*8-bit full adder code verilog)
multiplication
- 用C语言实现两位小于1的二进制小数的原码一位乘法。 1. 首先设置两个真值的输入形式为字符串，这样便可以输入正负号和小数点。 2. 程序将两个字符串中的0和1提出存入整形数组 3. 分别提前编写好两个整形数组的相关函数。例如：数组输出函数、全加器函数、右移函数等等。 4. 按照流程图，定义B，C，A数组，长度均为N，N值在开头用define定义。长度N要尽可能设置大一些。 5. 按照流程图的结构，设置循环，判断等结构。最终计算出最后结果真值。(Using C language to a
quartuswork
- vhdl入门实例，一位全加器和一位半加器的quartus9.1程序，可直接运行(VHDL entry examples, a full adder and a half adder quartus9.1 program, can be run directly)
UTS JST Delta Rule
- input full adder and by using delta rule algorithm
serial_adder
- 串行加法器的vhdl描述，用两个移位寄存器和一个全加器，一个d触发器实现(The VHDL descr iption of the serial adder, with two shift registers and a full adder, a D trigger)