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edashiyan
- 一个简易的带进位的全加器实现，希望能对大家有益-Into place a simple full adder implementation, hope it' ll be useful
fulladder
- simulation full adder using vhdl-simulation full adder using vhdl
fulladder
- 由四位全加器通过元件例化语句设计成十六位的全加器-By four full adder component instantiated by statements designed 16 of the full adder
4weiquanjia
- 用VHDL写的4位全加器,5.1版本编写的-Use VHDL to write four full adder, 5.1 version of the written
sourcecode
- bit adder full adder upcounter encoder multiplier
fadder32
- 短代码实现32位全加器，带经Quartus II9.1编程测试全部文件-Short code to achieve 32-bit full adder, with programming tested by the Quartus II9.1 all documents
3bit_adder
- Verilog source code for a 3bit full adder build with modules using predefined nand gates.
vhdlcoder
- 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。 二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可
VHDL
- 译码器。半加器，全加器。。。包括源程序和仿真波形-Decoder. Half adder, full adder. . . Including the source and the simulation waveform
07401200310
- VHDL原程序包括译码器，半加器，全加器-VHDL program, including the original decoder, the half adder, full adder
fulladder
- vhdl code for full adder program using libero software.
adder4
- 此源代码是基于Verilog语言的4 位全加器，4 位计数器、 4 位全加器的仿真程序、4 位计数器的仿真程序是用EDA语言描述4 位全加器，有广泛的应用。-The Verilog language source code is based on the 4-bit full adder, 4 bit counter, 4-bit full adder simulation program, 4-bit counter of the simulation program is to use la
ADD6
- 此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。-This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to ac
full_adder
- 通过运用quartusii运用vhdl语言描述一个全加器的设计程序-Vhdl language through the use of quartusii used to describe a full adder design process
full_adder
- 4 bit Full adder: addes two 4 bit numbers
alu
- 实现五位加法器功能，还有ALU的程序模块！同时有四位全加器的功能模块！-Adder to achieve five functions, as well as program modules ALU! At the same time there are four full-adder modules!
Desktop
- it s a file contain Verilog code of a full adder. I hope this file is usefull for someone ! Regards !
Case_Study_FA
- This document objective is to design a one bit full adder to be used as part of a serial adder.-This document objective is to design a one bit full adder to be used as part of a serial adder.
sy4
- 用VHDL语言设计了一个8位2进制全加器-VHDL language design with an 8-bit binary full adder 2
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.