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i2c_master_slave_core.tar
- I2C verilog HDL code including test environment
Verilog-testbench-and-memory-I2C
- verilog编写的测试平台，内含具体project和储存模块的编写-Verilog testbench for digital design Memory I2C module Assignment
I2C
- K2FPGA开发板实验教程——I2C协议说明及verilog实现读写I2C器件，中文内涵代码，验证可用。-K2FPGA development board test tutorial- I2C protocol descr iption and verilog read and write I2C devices, Chinese connotation code to verify availability.
i2c
- i2c code in Verilog , with master and slave it will help user for his work and interface design using i2c
i2c-master
- I2C Master Code in Verilog using Finite State Machine.
I2C
- verilog实现i2c在总线协议，包括主机和从机，很全面的，费了好大劲整理的-discr iption of i2c protocol
I2C
- Verilog语言实现I2C通信功能，可直接作为模块用于自己工程中。-Verilog language I2C communication functions can be used directly as a module for their own projects.
i2c-master
- i2c 总线 host 控制器 ， fpga上验证过，可以实现i2c 通信。-verilog IP for i2c master controller
FPGA-Verilog-I2C
- FPGA描述I2C协议过程，采用Verilog语言编写，压缩包里含有完整的代码（已经综合仿真），仿真图-FPGA I2C protocol process descr iption, using Verilog language, compressed bundle contains the complete code (already integrated simulation), simulation map
proyecto-I2C
- It s a VERILOG code to initiate a I2C protocol on an FPGA and an EEPROM of 512 KB
i2c
- fpga verilog IIC 已经调试通过-fpga verilog IIC
i2c
- i2c从机可综合verilog代码，并包含简单主机，寄存器组。-i2c slave synthetic behave verilog code, including simple master and registers.
I2C(8bit)
- 用verilog实现的I2C通讯模块程序，结构非常清晰，已多次应用于实际项目中-I2C communication module with verilog program implemented, the structure is very clear and has been repeatedly used in actual projects
i2c_testbench
- i2c verilog rtl with testbench very good code and works perfectly with cadence ius and ncverilog
traffic-light-Verilog
- 交通灯分为X组和Y组，每组包括了2位倒计时数码管和红黄绿三色LED信号灯（每组包括﹢、-两小组，显示内容一样），考虑到应用需求，要求芯片可通过I2C接口连接到上位机，以调节内部控制寄存器,此为Verilog代码，包含led、seg、timer等模块。-Traffic lights are divided into groups X and Y groups, each including two digital countdown yellow-green and red LED lights
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
i2c_master_slave_latest.tar
- i2c master slave VHDL code
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
I2C总线协议中文版PDF
- fpga的I2C设计文档，VERILOG语言，I2C协议(FPGA I2C design documents, VERILOG language, I2C protocol)
i2c_latest.tar
- 基于verilog的I2C接口协议代码，支持EEPROM(Verilog based I2C interface protocol code, support EEPROM)