搜索资源列表
verilog-master-files
- Verilog master files of AMBA axi interface
rtc_interface
- 该段代码给移植到黑金DB2C5开发板上面的RTC接口verilog代码，已经经过实验验证。-This code to transplant to black gold DB2C5 development board above RTC interface verilog code, has been experimentally validated.
verilog-uart
- UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
uart_Verilog
- uart接口verilog源码，实现数据串并行的转换。内容包含十个代码文件。-uart Interface verilog source of data for serial-parallel conversion. Contains ten code files.
Verilog-interface
- 基于fpga的verilog语言 实现的串口接收发送数据编程-fpga serial
vga_lcd.tar
- VGA LCD Interface Verilog Design
CF-verilog
- CF卡的经典整套资料，有芯片手册、接口说明、verilog源码、参考电路，很适合FPGA开发者研究CF卡-Classic set of data on the CF card with a chip manuals, interface descr iption, verilog source code, reference circuit, it is suitable for FPGA developers to study the CF card
ADS58c23_spi
- ads58c23的SPI接口verilog-ads58c23 SPI interface verilog
fsmc
- 修改过的icore2复用模式ARM与FPGA FSMC接口 Verilog的-Modified icore2 multiplexed mode ARM and FPGA FSMC Interface Verilog s
DDS9912
- AD9912芯片的接口控制程序，SPI通信方式Verilog编写-AD9912 interface Verilog
1---Serial-interface-(RS-232)
- Verilog HDL编写的RS232通信接口，包含RS232接口通信原理解析和编程实现文档-Verilog HDL prepared by the RS232 communication interface, including RS232 interface communication principles of parsing and programming documents
cp_model
- 原创协处理模型，异步并行接口，verilog实现，可作为仿真testbench用 -Co-processing model, asynchronous parallel interface, verilog achieve, can be used as a simulation testbench
verilog
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
adc.v
- this an adc interface verilog code-this is an adc interface verilog code
UART-master
- UART通讯接口verilog代码实现，uart_tx子模块和uart_rx子模块，包含详细testbench-UART interface verilog code, uart_tx、uart_rx， testbench
FPGA-VGA-interface-code
- 针对显示器VGA接口通信FPGA的Verilog源代码，主要包括VGA行扫描和帧扫描模块-Verilog source code for communication VGA interface communication, including VGA line scan and frame scan module
traffic-light-Verilog
- 交通灯分为X组和Y组，每组包括了2位倒计时数码管和红黄绿三色LED信号灯（每组包括﹢、-两小组，显示内容一样），考虑到应用需求，要求芯片可通过I2C接口连接到上位机，以调节内部控制寄存器,此为Verilog代码，包含led、seg、timer等模块。-Traffic lights are divided into groups X and Y groups, each including two digital countdown yellow-green and red LED lights
6IIS.tar
- IIS接口的verilog代码，用verilog编写，片上系统SOC源代码分析的IIS接口代码，总线是wishbone-IIS interface verilog code
Zet-1.3.1
- 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 int
外设控制入门篇09：PS2接口控制实验
- ps2接口的简单测试与功能演示代码 已经测试过的(ps2Ps2 interface simple and functional demo code has been tested)