搜索资源列表
spi_master
- SPI通信：串行flash的读写擦除命令通过SPI接口进行通信。? CPU芯片与FPGA通过SPI接口进行通信。? 其他功能集成电路芯片参数寄存器配置。例如DAC芯片内部有很多寄存器（因为芯片有很多功能，要通过设置寄存器不同的开关来打开或关闭相应的功能，一上电去初始化寄存器）需要我们去配置。FPGA一上电也是通过配置芯片里边来读取数据，然后配置FPGA内部的SRAM。FPGA是读取FLASH里边的串行数据，读取完校验完才配置到我们的FPGA的SRAM中去。速度比串口快，而且是同步传输。(Th
i2c_master_module
- i2c接口的fpga实现，工作在master模式下，verilog(The FPGA implementation of the I2C interface, working in the master mode, verilog)
i2s_top
- i2s接口fpga实现，工作在主模式，ISE和vivado下已验证(I2S interface FPGA implementation, working in the master mode)
CH14_RGMII_UDP_TEST
- 用xilinx的SPARTAN6 实现的UDP，可通过PC机网络抓包工具进行发送和接收，增加了网络视频传输的接口，具有很好的参考价值(With the Xilinx implementation of the SPARTAN6 UDP, can be sent and received through PC network capture tools, increase the network video transmission interface, has a good reference
spiflash
- SPI接口实现，对SPI写，擦出等功能操作，此代码在板子上进行验证过，没有任何问题(SPI interface implementation, write to SPI, wipe out and other functional operations, this code has been verified on the board, there is no problem.)
UART
- Verilog写的UART 协议。可用于FPGA RS232接口实现。(The UART protocol written by Verilog. It can be used for the implementation of the FPGA RS232 interface.)
qspi
- qspi接口控制，指令包括spi、dual spi、quad spi，通过验证，供参考(Qspi interface control, including spi, dual spi, quad spi, for reference.)
uart
- uart串口FPGA实现示例 example(uart serial interface example)
clocking
- 很好的时钟接口程序，可用于时钟驱动的程序，便于开发者使用(Good clock interface program for clock - driven programs for developers to use.)
uart
- UART接口的基于FPGA芯片，用Verilog语言实现，在quartus上操作(UART interface is implemented by FPGA)
uart_55x_lite
- 本模块设计仿照ST16C554芯片，特点如下： a) Localbus总线接口； b) 多通道设计，最大通道数为4，实际通道数可配置； c) 两种中断方式，支持电平中断、沿中断；(The module is designed and modeled on ST16C554 chip. A) Localbus bus interface; B) multi-channel design. The maximum number of channels is 4, and the numbe
dds_PIO
- 利用QSYS中自带的PIO接口实现DDS模块(Using the PIO interface in QSYS to implement the DDS module)
ARM_SOC
- ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker
dma_ahb_latest.tar
- AHB DMA verilog源码 AHB总线 DMA接口源码(AHB bus DMA interface source code)
i2s_interface
- verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)
xapp495(1)
- 实现HDMI的receiver和transmitter，来源xilinx xapp(Implement HDMI interface 1.0, including receiver and transmitter,from Xilinx xapp)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
通信协议FPGA
- 本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8 位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface
CDCM6208_SPI
- 完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)
hdmi
- 滚动彩条显示。通过HDMI接口输出单色图案、渐变色、单幅马赛克、动态马赛克等图案。使用Verilog，基于Xilinx Spartan-6 LX45器件，AX6045开发板(Scroll bar display. Through HDMI interface output monochrome pattern, gradient color, single mosaic, dynamic mosaic and other patterns. Using Verilog, based on Xil