搜索资源列表
FFT
- verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
linux_transplantation
- 《S3C44B0开发板移植内核2.6 uclinux记录》以及一篇论文《基于Linux的USB 2.0 OTG IP核主机驱动的研究与实现》。-" S3C44B0 development board transplantation kernel 2.6 uclinux record" and a paper " Linux-based USB 2.0 OTG IP core host-driven research and implementation."
USB_IP-CORE-design
- USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
ip_core
- 一些FPGA上用的到的IP核,种类非常全,开发小的ASIC基本上够用了-To use some of the FPGA IP cores, species are very full, the development of ASIC basically small enough
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
USB2.0-IP
- USB2.0 IP核源代码，经典好用！写这么多真没意思！-USB 2.0 IP core source code, easy to use classic! Write so really boring!
IP-coreincluding-VHDL-and-Verilog
- 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
vga_lcd
- VGA/LCD控制 ip核，支持 CRT LCD,支持多种色彩方案。-VGA/LCD control ip core, support CRT LCD, supports a variety of color schemes.
IP(1)
- 全功能硬件扫描键盘控制器IP核的实现，属于比较前沿的的键盘扫描方法-The realization of the full-featured hardware scanning keyboard controller IP core, belonging to compare the forefront of keyboard scan
CAN-Bus-IP-Core
- ＦＰＧＡ中ＣＡＮ总线的ＩＰ核，加入工程中既可以使用。-CAN bus in FPGA IP, can be used to join the project
SPI-IP
- 比较经典实用的ip核，对初学者有很大的帮助，语言比较简单。-Classic and practical IP core, a great help for beginners, the language is relatively simple.
IP-Release-Notes-Guide
- 该文件包含xilinx 公司发布的所有IP CORE的介绍，比较全面。-This file contains all the company released xilinx IP CORE presentation, more comprehensive.
FPGA-IP
- FPGA的宏模块介绍，主要是IP核的应用简单介绍-FPGA macro module introduces mainly the application of IP core brief
PCIIP-core
- 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generatio
UART-IP-based-on-queue
- 基于队列传输的UART的IP核程序，已调试可直接使用。-Queue-based transmission of UART IP core procedures have been debugging can be used directly.
altera-tse-ip
- MegaWizard_Plug-In工具生成altera三速以太网IP核并编译仿真-MegaWizard_Plug-In tool to generate altera Triple Speed Ethernet IP Core and compile simulation
UART-to-Bus-Core-Specifications
- The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. This core can be used during initial board debugging or as a permanent solution when high speed interfaces are not required. The i
CAN-IP
- CAN控制器IP核(可直接在Nios II中使用)-CAN controller IP core (Nios II can be used directly in the middle)
LCD-IP-CORE
- LCD Controller IP for Xilinx FPGA
cordic_ds249
- FPGA开发过程中的IP核，用于计算正弦，余弦和正切等。(IP core used in FPGA design to calculate cos and sin.)