搜索资源列表
ARMcore
- 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
fft
- 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
a8254
- 基于8254 ip 核的vhdl的实现以及对于quart 2的实现及应用-Based on the 8254 IP core of the realization of VHDL and for the implementation and application quart 2
SPI
- 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
BlockRAM
- xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
pci_core.tar
- vhdl 写的 PCI IP核程序，已经过测试-pci ip core
vga_game_demo
- 乒乓球游戏，基于Xilinx板子，并且有vga IP核，使用EDK进行编程-Table Tennis Games
freerisc8_11
- 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
8051core
- 8051 VHDL IP Core，有兴趣的可以-8051 VHDL IP Core, who are interested can
ramvhdllib_06
- The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
8051IP
- 8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.-8051 IP, the use of VHDL language descr iption, support intel s HEX format, including the interruption, such as timers.
I2C
- 详细描述了I2C的技术规范 版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed descr iption of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
firewire
- IP CORE .VERY GOOD AS A STUDY FILE-IP CORE. VERY GOOD AS A STUDY FILE
vhdl_source
- MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
8086IP
- 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
15Altera_IP
- 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN