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codefroge-ldpc-matlab
- this an implementation of ldpc encoder and decoder in matlab. generator matrix, parity check matrix and the chennel are implemented seperately. the bit error rate performance is estimated for the ldpc code -this is an implementation of ldpc encoder a
LDPC-code
- LDPC encoder and the decoder of sum-product algorithm. (input H matrix form is Mackay s website form)
put
- Efficient LDPC Decoder Implementation for DVB-S2 System
NBLDPC_GF16
- This a program implementing nonbinary LDPC decoder in wireless communications-This is a program implementing nonbinary LDPC decoder in wireless communications
ldpc-decoder-code
- Specify the decision method used for decoding as one of Hard decision | Soft decision . The default is Hard decision . When you set this property to Hard decision , the output is decoded bits of double or logical data type. When you set this property
ldpc-decoder-matlab
- Specify the condition to stop the decoding iterations as one of Maximum iteration count | Parity check satisfied . The default is Maximum iteration count . When you set this property to Maximum iteration count , the object will iterate for the number
LLR decoding for 64 QAM
- thiese programs very helpful in LLR decoding algorithm which is used in turbo code or LDPC decoder with 64 QAM modulation
Decoder-Optimised--Growth-
- 一种新型的建筑不规则低密度 奇偶检验基于所述修改（LDPC）码 渐进边增长（PEG）的算法。边缘 所述PEG算法的位置是由利用所述Sum-增强 积算法在奇偶校验矩阵的设计。该 提出的算法是在块长度和速度非常灵活。 被提议的方法构建代码的测试 AWGN信道和显著的性能改进 实现。建议解码器优化的灵活性 动作，然后由它的使用在修改所述改进的示 PEGIPEGI）算法来实现进一步的性能提升。-A novel construction for irregular
LDPC
- 实现LDPC编码仿真和译码仿真，参数有接收码字，解调器输出，信道噪声标准差，校验矩阵，迭代次数-realise the encoder and decoder of LDPC,ceremeters include receiveword,sigma,check parity,IterNum
minsum
- 二元ldpc译码器 min-sum算法 迭代次数固定 输入信号长度一帧512bits-binary ldpc decoder. min-sum algorithm。fixed iter number.512 bits/frame
LDPC_Decoder_SPA
- LDPC译码器，基于SPA算法，matlab函数。-LDPC decoder, based on sum-product algorithm. a matlab function
06018325
- A Nonbinary LDPC Decoder Architecture With Adaptive Message Control
XOR_tree
- This source code is a check node unit for LDPC decoder. The language is Verilog HDL.
LDPC-code
- LDPC encoder and the decoder of sum-product algorithm.(input H matrix form is Mackay s website form)
LDPC-code-Decoder
- Here are the base papers related to decoding algorithms for LDPC codes.
LDPC
- Parity check bits is computed using sparse LU decomposition, utilizing sparse matrix properties of H. LDPC code decoding is done using iterative belief propagation or sum-product algorithm (SPA). Four versions of SPA decoder are presented.
a2013_TCAS_NB-LDPC_decoder
- Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm
LDPC
- LDPC SIMULATION ENCODER AND DECODER
decodeBitFlip
- function vHat decodeBitFlipping(rx, H, iteration) Hard-decision/bit flipping sum product algorithm LDPC decoder rx : Received signal vector (column vector) H : LDPC matrix iteration : Number of iteration vHat : Decoded vector (
decodeLogDomain
- function vHat decodeLogDomain(rx, H, N0, iteration) Log-domain sum product algorithm LDPC decoder rx : Received signal vector (column vector) H : LDPC matrix N0 : Noise variance iteration : Number of iteration vHat : Decoded