搜索资源列表
Project3-Logisim
- 用logisim写的单周期CPU，可以跑MIPS汇编编译的二进制代码，测试完美通过，供学弟学妹参考，计算机组成原理试验-Logisim write cycle with a single CPU, you can run the MIPS assembler binary code, test perfect pass for mentees reference, computer composition principle test
s_pri
- check for trapped MIPS 46xx CPU, dump exception frame.
CPU1
- 一个简单的多周期的基于MIPS的CPU设计-cpu VHDL
xburst_core
- cpu mips的代码，很具有研究价值，是嵌入式开发的入手资料-it is good material for us to learn .............
irq_regs
- FRV per-CPU frame pointer holder.Just-In-Time compiler for BPF filters on MIPS.
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
sc_computer_2
- Verilog单周期CPU实现,可以实现简单的mips指令，附Verilog源码-Verilog achieve single-cycle CPU
project-1
- 计算机体系结构大作业请思考如何用C语言描述一个计算机系统？ 结构：CPU、Cache、主存、基本MIPS指令集 行为：多周期CPU，机器周期如图1.2所示 -Computer architecture project, please think about how to use C language to describe a computer system? structure: the CPU, Cache, main m
project-2
- 计算机体系结构大作业请思考如何用C语言描述一个计算机系统？ 结构：CPU、Cache、主存、基本MIPS指令集 行为：多周期CPU，机器周期如图1.2所示-Computer architecture project, please think about how to use C language to describe a computer system? structure: the CPU, Cache, main memo
project-3
- 计算机体系结构大作业请思考如何用C语言描述一个计算机系统？ 结构：CPU、Cache、主存、基本MIPS指令集 行为：多周期CPU，机器周期如图1.2所示-Computer architecture project, please think about how to use C language to describe a computer system? structure: the CPU, Cache, main memo
project-4
- 计算机体系结构大作业请思考如何用C语言描述一个计算机系统？ 结构：CPU、Cache、主存、基本MIPS指令集 行为：多周期CPU，机器周期如图1.2所示-Computer architecture project, please think about how to use C language to describe a computer system? structure: the CPU, Cache, main memo
project-5
- 计算机体系结构大作业请思考如何用C语言描述一个计算机系统？ 结构：CPU、Cache、主存、基本MIPS指令集 行为：多周期CPU，机器周期如图1.2所示-Computer architecture project, please think about how to use C language to describe a computer system? structure: the CPU, Cache, main memo
singleTcpu
- 单周期cpu设计，基于xilinx ISE环境设计，使用MIPS语言-Single cycle, the CPU is designed, based on xilinx ISE environment design, the use of MIPS language
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
soc_sram_func
- 利用verilog编写的32位 MIPS指令集CPU，sram接口，已上板验证(The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.)
bash 1.14.7 源代码
- bash 1.14.7 源代码，这个版本支持mips构架的CPU
openssl 3.0.0 源码
- 给mips构架cpu的路由器交叉编译用的，传一份。
bash 5.1 源代码
- 给mips构架cpu路由器交叉编译用的，自带的sh没功能，传一份。